error detection and correction

(redirected from Error detector)

error detection and correction

(algorithm, storage)
(EDAC, or "error checking and correction", ECC) A collection of methods to detect errors in transmitted or stored data and to correct them. This is done in many ways, all of them involving some form of coding. The simplest form of error detection is a single added parity bit or a cyclic redundancy check. Multiple parity bits can not only detect that an error has occurred, but also which bits have been inverted, and should therefore be re-inverted to restore the original data. The more extra bits are added, the greater the chance that multiple errors will be detectable and correctable.

Several codes can perform Single Error Correction, Double Error Detection (SECDEC). One of the most commonly used is the Hamming code.

At the other technological extreme, cuniform texts from about 1500 B.C. which recorded the dates when Venus was visible, were examined on the basis of contained redundancies (the dates of appearance and disappearance were suplemented by the length of time of visibility) and "the worst data set ever seen" by [Huber, Zurich] was corrected.

RAM which includes EDAC circuits is known as error correcting memory (ECM).

[Wakerly, "Error Detecting Codes", North Holland 1978].

[Hamming, "Coding and Information Theory", 2nd Ed, Prentice Hall 1986].
References in periodicals archive ?
The MP1800A also provides a built-in High Sensitivity Error Detector (ED) with best-in-class input sensitivity and fast Auto Adjust function.
The SSB32 system contains a serial BERT controller (SSB16000 or SSB16000J) and pattern generator (PG32) and error detector (ED32) remote-mountable heads.
The J-BERT error detector can now ignore SKP ordered sets when counting errors, even when they deviate from the original length sent out by the pattern generator.
Quotation are invited for procurement of Temperature control system kit,Potentiometer error detector,Linear system simulator,Pulse oximeter with adult finger probe,Short wave diathermy,Ultrasound therapy unit,Module for design of EEG acquisition system,Modules for design of EOG acquisition system,Modules for design of PCG acquisition system,Modules for design of human temperature measurement system
In addition to incorporating a PPG for outputting high-quality, high-amplitude signals, the MP1800A features an Error Detector (ED) module with high input sensitivity to support signal analyses, including burst pattern, Bathtub Jitter and EYE Diagram measurements.
The SSB17 system contains a serial BERT controller (SSB16000 or SSB16000J) and full-rate pattern generator (PG17) and error detector (ED17) remote mountable heads.
The pattern generator and error detector, which operate at full rate speed without external multiplexers or demultiplexers, are configured as small remotely mountable heads.
Anritsu today introduced a high-sensitivity error detector and other additions to its MP1800A BERT (Bit Error Rate Tester) signal quality analyser to support multi-channel BER measurements up to 32.
The MP1800A features an internal pulse pattern generator (PPG) and high-input-sensitivity error detector (ED) module, each of which can be configured with one, two, or four channels to support multi-channel synchronization of up to eight channels at 32 Gbit/s.
The MP1800A features an internal pulse pattern generator (PPG) and high-input-sensitivity error detector (ED) module, each of which can be configured with one-, two-, or four-channels to support multi-channel synchronization of up to eight channels at 32 Gbit/s.
The introductions include the LE320, a 2 differential channel, 9 tap Linear Equalizer supporting data rates up to 32Gbps as part of a BERTScope receiver test system; new options for the PPG/PED multi-channel BERTs that provide signal impairments and output adjustment at data rates up to 32Gbps, as well as, a new 40Gbps error detector model; and Option CEI-VSR that automates the DSA8300 Sampling Oscilloscope to perform required compliance tests for the CEI-28G-VSRstandard.