EEPROM

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EEPROM

[¦ē′ē‚präm]

EEPROM

EEPROM

(Electrically Erasable Programmable Read Only Memory) A rewritable storage chip that holds its content without power. EEPROMs are byte addressable but must be erased before being rewritten. In flash memory, which evolved from EEPROMs and is almost identical in architecture, an entire block of bytes must first be erased. In addition, EEPROMs are typically used on circuit boards to store small amounts of instructions and data, whereas flash memory modules hold gigabytes of data for camera and computer storage (see flash memory). EEPROMs store location data in LTO tape cartridges, and they are actually used in flash memory-based SSDs; not as data storage but as boot code. See LTO.

A Floating Gate Holds the Charge
The bit cells in EEPROM and flash memory are CMOS-based transistors that hold a charge on a "floating gate." With no charge on the floating gate, the transistor acts normally, and a pulse on the control gate causes current to flow. When charged, it blocks the control gate action, and current does not flow. Charging is accomplished by grounding the source and drain terminals and placing sufficient voltage on the control gate tunnel through the oxide to the floating gate. A reverse voltage channeled from another transistor clears the charge by causing it to dissipate into the substrate.

EEPROMs have a lifespan of between 10K and 100K write cycles, which is considerably greater than the EPROMs (single "E") that preceded them. See EPROM, SEEPROM, memory types and flash memory.


The Floating Gate Transistor
EEPROM and flash memory cells use a transistor with a floating gate that holds a charge. When charged, the action of the control gate is impeded, and the charged/uncharged state determines the 0 or 1 content of the bit.







The Erase Circuit
The floating gate transistor stores the charge, and a regular MOS transistor is used to erase it. Most EEPROMs are byte erasable with one MOS transistor for every eight floating gate transistors. Flash memory uses only one MOS transistor to erase an entire block of floating gate transistors.
References in periodicals archive ?
The other transistor uses high drain voltages to induce the HEI mechanism in order to increase the electron charge onto the floating gate. Nevertheless, the thin oxide layer tends to degrade with the use of the cell.
The increase in the number of bit error rate with increasing the absorbed dose can be attributed to the effects of tunnel oxide radiation and oxide which separates the floating gate in the cell of flash memory.
As shown in Figure 9, silicon nanocrystal NVM replaces conductive polysilicon floating gate charge storage layer of standard flash memory with discrete and mutually isolated charge storage nodes in silicon nanocrystals distributed in control oxide layer [38-41].
Erasing the floating gate involves connecting the drain diffusion to ground, and applying the positive voltage to the source, thereby causing band-to-band tunneling (BBT) generation of holes and their injection into the FG.
The charge is stored on isolated nanocrystals and is lost only from those few nanocrystals that align with detects in the tunnel oxide--while the same defects in a conventional floating gate device would result in significant charge (and thus data) loss.
Charge is stored on floating gates, and heat coupled with a loss of charge can cause a "bit-flip." Is this a significant problem?
Since SSDs use flash memory which use floating gate transistors to store data instead of using the magnetic way used by traditional hard disk drives, SSDs don't get affected by magnetism through regular magnets.
The collapse of GaN FETs is a dramatic effect of this behaviour of n-GaN surfaces that is capable of forming a negative floating gate on the surface of these devices [13, 15].
In both EPROMs and EEPROMs, the floating gate is used to store charge and thus maintain a logical state.
The contributors propose a fast algorithm for the chirp rate estimation, a bi-directional gate using pseudo floating gate, a visual notation for processor and resource scheduling, and improved policies for drowsy caches in embedded processors.
Hot electron injection describes the diversion to the floating gate of electrons flowing from source to drain.
These are non-volatile and use a single floating gate that is charged or discharged to set the state of a switch between two metal lilies am so they do not need a bitstream for configuration.