front side bus

(redirected from Frontside bus)

front side bus

(FSB) The bus via which a processor communicates with its RAM and chipset; one half of the Dual Independent Bus, the other half being the backside bus. The L2 cache is usually on the FSB, unless it is on the same chip as the processor In PCI systems, the PCI bus runs at half the FSB speed.

Intel's Pentium 60 processor used a bus speed and processor speed of 60 MHz. All later processors have used multipliers to increase the internal clock speed while maintaining the same external clock speed, e.g. the Pentium 90 used a 1.5x multiplier. Modern Socket 370 motherboards support multipliers from 4.5x to 8.0x, and FSB speeds from 50 MHz to a proposed 83 MHz standard. These higher speeds may cause problems with some PCI hardware.

Altering the FSB speed and the multiplier ratio are the two main ways of overclocking processors.

Toms Hardware - The Bus Speed Guide.

Toms Hardware - The Overclocking Guide.
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6GHz con un FrontSide Bus (FSB) de 800MHz, 512KB de memoria cache L2.
The GeForce 7150, 7100, and 7050 mGPUs are designed to support a full range of Intel CPUs (Core 2, Pentium, and Celeron CPU families), including upcoming 45nm Intel "Penryn" processors and other new features, such as 1333MHz frontside bus technology.
The new chip also supports the 2GHz HyperTransport frontside bus which was introduced by AMD on their latest Athlon 64 chips.
The chipsets support VIA's favored PC133 SDRAM memory connection standard and use a 133MHz frontside bus.
The chips support AMD's Socket 7 and Super 7 architecture, as well as a 100-MHz frontside bus.
Intel's own Camino chipset, also called the 820, along with the 810e version for Celeron systems, will feature a 133MHz frontside bus, to which motherboard designers will be able to connect PC-133 DRAM if they wish.
However, while Whitney's 100MHz memory interface demands PC100 SDRAMS, the Celeron can only access the external world through a 66MHz frontside bus, meaning that Whitney makes calls at 66MHz only to raise them to 100MHz, causing additional dissipation through synchronization.