Futurebus+

Futurebus+

An IEEE standard multisegment bus that can transfer data at 32, 64, 128 and 256-bits and can address up to 64 bits. Clock speeds range from 25 to 100MHz. At 100MHz and 256 bits, it transfers 3.2 Gbytes/sec.
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These devices are designed for medium-slot, medium- and heavily-loaded backplanes, fully support live insertion and can increase data backplane throughput by 100% to 300% over traditional logic, such as ABT, FCT, LVT, ALVT, LVC and FutureBus+ according to the company.
Applications of the symbolic model checking method have been limited in the literature to the verification of the snooping protocols of the Gigamax [McMillan and Schwalbe 1991] and of the Futurebus+ [Clarke et al.
1993b] the results of applying the SMV to the verification of the Futurebus+ protocols are given.
The initial backplanes used will be IEEE 1014 Versa Module Eurocard bus (VMEbus) with growth projected to Futurebus+ (IEEE 896).
Moreover, VITA is committed to Futurebus+ as an IEEE Computer Society standard for the next-generation computer backplane.
According to sources in the field, our (1)competitors have been unable to deliver Futurebus+ products in a timely manner, due to the fact that some have already reached full production capacity, while others aren't far behind.
According to Noriyuki Minegishi, Senior Engineer, "Our charter is the development of advanced Futurebus+ chips of the highest quality and reliability to meet the requirements of our systems and the needs of our customers.
Personal computers, small form factor disk drives, pagers, cordless telephones, Futurebus+ daughtercards, portable instruments, and bar code scanners are just a few of the numerous electronic products that are now demanding more compact interconnect solutions and are ideal applications for Berg's Minitek 2.