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[¦haf ¦ad·ər]
A logic element which operates on two binary digits (but no carry digits) from a preceding stage, producing as output a sum digit and a carry digit.


An elementary electronic circuit in the arithmetic logic unit (ALU) that adds one bit to another. The output is the result bit and the carry bit. Just like 9 + 1 derives 0 with a carry of 1, in binary, 1 + 1 yields the same results. See binary and ALU.

INPUTS     OUTPUTSBit Bit  Result  Carry1   2    Bit     Bit

   0 + 0  =  0     0

   0 + 1  =  1     0

   1 + 0  =  1     0

   1 + 1  =  0     1
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References in periodicals archive ?
In this gate the second output is equal to A[direct sum]B which is the sum output of the half-adder circuit and if C = 0 then the third output is equal to "A.
The design of PASTA using dual gate MOSFET is fixed and uses half-adders (HAs) along with multiplexers requiring least interconnections.
The interior structure of the incrementation block, which comprises a sequence of half-adders (HAs), is shown in Figure 3.