Harvard architecture


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Harvard architecture

(architecture)
A computer architecture in which program instructions are stored in different memory from data. Each type of memory is accessed via a separate bus, allowing instructions and data to be fetched in parallel.

Contrast: von Neumann architecture.

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Harvard architecture

A computer architecture in which the program's instructions and the data reside in separate memory banks that are addressed independently. Named after the Mark I computer at Harvard University in the 1940s, a pure Harvard architecture can execute instructions and process data simultaneously, because each has its own address bus.

Microcontrollers, which have separate program and data memory banks (flash memory and RAM), often adhere to the Harvard architecture model and provide simultaneous overlap. However, most computers use the von Neumann architecture and employ CPU caches to achieve overlap (see cache). Contrast with von Neumann architecture. See Mark I and address bus.


Microchip Microcontrollers
This diagram shows how the two memory banks are addressed independently for simultaneous instruction execution and data processing. (Image courtesy of Microchip Technology Inc., www.microchip.com)
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References in periodicals archive ?
The Super Harvard Architecture Computer (SHARC) chip is a monolithic processing subsystem consisting of 26 million transistors and 512 kB of on-chip static random access memory.

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