Harvard architecture


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Harvard architecture

(architecture)
A computer architecture in which program instructions are stored in different memory from data. Each type of memory is accessed via a separate bus, allowing instructions and data to be fetched in parallel.

Contrast: von Neumann architecture.

Harvard architecture

A computer architecture in which the program's instructions and the data reside in separate memory banks that are addressed independently. Named after the Mark I computer at Harvard University in the 1940s, a pure Harvard architecture can execute instructions and process data simultaneously, because each has its own address bus.

Microcontrollers, which have separate program and data memory banks (flash memory and RAM), often adhere to the Harvard architecture model and provide simultaneous overlap. However, most computers use the von Neumann architecture and employ CPU caches to achieve overlap (see cache). Contrast with von Neumann architecture. See Mark I and address bus.


Microchip Microcontrollers
This diagram shows how the two memory banks are addressed independently for simultaneous instruction execution and data processing. (Image courtesy of Microchip Technology Inc., www.microchip.com)
References in periodicals archive ?
A super Harvard architecture can be used when there are separate instruction and data memory banks.
The microcontroller leverages a Harvard architecture with 16-bit index registers and stack pointer, a 16Mbyte linear address space, advanced addressing modes, and other features designed to optimally support C-programming to deliver leading-edge CPU performance in both speed and code density.
DOREEN Lawrence is to achieve her dream of sending six underprivileged students on a Harvard architecture course in her murdered son's name.
The Super Harvard Architecture Computer (SHARC) chip is a monolithic processing subsystem consisting of 26 million transistors and 512 kB of on-chip static random access memory.
The 32-bit CISC RX core has Harvard architecture and a 5-stage instruction pipeline which achieves a RISC-like rate of one clock per instruction.
Specifically, CISC features such as variable-byte instructions are combined with RISC features such as general register machine, Harvard architecture, and five-stage pipeline.
Cyborg Civics', William Gibson, Harvard Architecture Review, vol 10, 1998, p173.
An advantage of the Harvard architecture over the Von Neumann architecture for space-based applications is that the program memory may be supported with special memory upset protection techniques.
The SH72546R is built around the SH-2A high-performance CPU core, which has a superscalar that enables it to execute two instructions simultaneously and a Harvard architecture.
The new CPU is based on a Harvard Architecture, which provides separate address and data paths, allowing the execution of instructions and data access in single cycle.
Using a traditional Harvard architecture, it features separate local, tightly coupled, instruction and data RAMs to eliminate memory contention and provide fast performance on performance-critical code and interrupt handling routines.

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