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A high-speed interconnection architecture between integrated circuits, introduced in 2001. Code-named Lightning Data Transport and developed by AMD and others, the HyperTransport I/O Link Specification defines a protocol and electrical interface between the CPU, memory and peripheral devices.

Since its introduction, HyperTransport's maximum aggregate bandwidth of 32-bit links progressed from 12.8 to 41.6 Gbytes/sec. Version 3.0 also added dynamic link splitting under software control. Called "Un-Ganging," it enables a single unidirectional link to be split into two; each at half the original bit width. HyperTransport (HT) was designed to be fully compatible with legacy PCI (running at 33 or 66 MHz) plus PCI Express and PCI-X technologies. For more information, visit the HyperTransport Consortium at www.hypertransport.org.
HYPERTRANSPORT VERSION               HT 1.x   HT 2.0   HT 3.0Feature        (2001)   (2004)   (2006)

 Clock speed    800 MHz  1.4 GHz  2.6 GHz

  (GB/sec)       12.8     22.4     41.6

 Hot pluggable   No       No       Yes

 Un-Ganging      No       No       Yes
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Applications and implementations include SAS-2, SATA-2, RapidIO, Aurora, RocketIO, Myrinet, PCI-Express, Hyper Transport, XAUT, and OIF-CEI copper ports.
Edited by Zeid Nasser DTK Computer Middle East, part of DTK worldwide network of branch offices and a leading brand of personal computers, notebooks and servers, has announced the Middle East launch of the "Racer SSS Gaming Station" that will provide gaming enthusiasts an ultimate experience with its AMD powered Athlon processor with Hyper Transport Technology for outstanding performance.
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5 includes significant productivity and technology enhancements targeted at emerging SERDES interconnect standards such as PCI-Express, Hyper Transport, XAUI and SATA/SAS.
These embedded processors deliver performance with up to 16 Lane Hyper Transport support and 9W to 35W TDP.
Hyper Transport Consortium -- VMETRO -- LeCroy Corporation -- Wavecrest -- Mentor Graphics
Alliance's product lines include PulseCore mixed signal products, SiPackets' family of high performance chip-to-chip interconnects based on the Hyper Transport technology, SRAMs (Static Random Access Memory) and PSRAMs (Pseudo Static Random Access Memory).