instruction set

(redirected from Instruction set architectures)

instruction set

[in′strək·shən ‚set]
(computer science)
Also known as instruction repertory.
The set of instructions which a computing or data-processing system is capable of performing.
The set of instructions which an automatic coding system assembles.

instruction set

(architecture)
The collection of machine language instructions that a particular processor understands.

The term is almost synonymous with "instruction set architecture" since the instructions are fairly meaningless in isolation from the registers etc. that they manipulate.

instruction set

The group of machine language instructions that a computer can follow, which may range from a handful to several hundred. It is a fundamental architectural component of a CPU and is either built into the CPU or into microcode, a layer between the instruction set and the circuitry. The instruction length is generally from one to four bytes long. See CISC, RISC, machine language, microcode and CPU.
References in periodicals archive ?
CCIX allows processors based on different instruction set architectures to extend their cache coherency to accelerators, interconnect, and I/O.
x86 is a family of backward compatible instruction set architectures, based on the Intel 8086 CPU and its Intel 8088 variant.
NASDAQ: MIPS) has announced a major release of the MIPS(R) architecture, encompassing the MIPS32(R), MIPS64(R) and microMIPS instruction set architectures.
Its anti tamper solutions are based on its TrustGUARD security processors that pioneered the concept of random instruction set architectures that are unique for each device.
Complex instruction set architectures were primarily motivated by a desire to reduce the "semantic gap" between the machine language of the processor and the high-level languages in which people were programming.
For the first time in the industry, a single interconnect technology specification will ensure that processors using different instruction set architectures (ISA) can coherently share data with accelerators and enable efficient heterogeneous computing significantly improving compute efficiency for servers running data center workloads.

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