JK flip-flop

JK flip-flop

(hardware)
An edge triggered SR flip-flop with extra logic such that only one of the R and S inputs is enabled at any time. This prevents a race condition which can occur when both inputs of an RS flip-flop are active at the same time. In a JK flip-flop the R and S inputs are renamed J and K. The set input (J) is only enabled when the flip-flop is reset and K when it is set.

If both J and K inputs are held active then the outputs will change ("togle") on each falling edge of the clock. JK flip-flops can be used to build a binary counter with a reset input.

http://play-hookey.com/digital/logic7.html.

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References in periodicals archive ?
Low Power and High performance JK Flip-Flop using 45 nm Technology" International Journal of Engineering Research in Electronics and Communication Engineering (IJERECE) 3(10): 26-29, ISSN: 2394-6849.
The counter in our design is implemented by NAND gates and jk flip-flops.
Since counter operates at relatively low frequencies, JK flip-flops are made of TSPC flip-flops.