Joint Test Action Group


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Joint Test Action Group

(architecture, body, electronics, integrated circuit, standards, testing)
(JTAG, or "IEEE Standard 1149.1") A standard specifying how to control and monitor the pins of compliant devices on a printed circuit board.

Each device has four JTAG control lines. There is a common reset (TRST) and clock (TCLK). The data line daisy chains one device's TDO pin to the TDI pin on the next device.

The protocol contains commands to read and set the values of the pins (and, optionally internal registers) of devices. This is called "boundary scanning". The protocol makes board testing easier as signals that are not visible at the board connector may be read and set.

The protocol also allows the testing of equipment, connected to the JTAG port, to identify components on the board (by reading the device identification register) and to control and monitor the device's outputs.

JTAG is not used during normal operation of a board.

JTAG Technologies B.V..

Boundary Scan/JTAG Technical Information - Xilinx, Inc..

Java API for Boundary Scan FAQs - Xilinx Inc..

JTAG Boundary-Scan Test Products - Corelis, Inc..

"Logic analyzers stamping out bugs at the cutting edge", EDN Access, 1997-04-10.

IEEE 1149.1 Device Architecture - Boundary-Scan Tutorial from ASSET InterTech, Inc..

"Application-Specific Integrated Circuits", Michael John Sebatian Smith, published Addison-Wesley - Design Automation Cafe.

Software Debug options on ASIC cores - Embedded Systems Programming Archive.

Designing for On-Board Programming Using the IEEE 1149.1.

Built-In Self-Test Using Boundary Scan by Texas Instruments - EDTN Network.
References in periodicals archive ?
1 boundary scan standard (commonly known as JTAG, after the Joint Test Action Group which defined the original specification).
Based on proven IDT pre-processing technology, and leveraging the sRIO, Joint Test Action Group (JTAG) and Inter-Integrated Circuit (I2C) interconnect standards, the IDT CPS-16 (80KSW0002AR) switch provides an advanced feature set developed in conjunction with IDT customers to meet their specific interconnectivity needs.
2 suite provides embedded systems developers with a complete, integrated tool solution that includes an integrated development environment (IDE), debugger, profiler, compiler, unified modeling language (UML) tools, Joint Test Action Group (JTAG) connection device and prototyping tools.
Other innovative functions include the sleep mode, which allows the product to minimize power consumption by placing the part in full standby mode without any input-level restrictions, and a Joint Test Action Group (JTAG) interface that allows designers to improve manufacturability with enhanced board debug and production diagnostics.
Typically, boundary scan, which is commonly referred to as JTAG from the group that defined the specification, the Joint Test Action Group, only tests DC-coupled device networks on a PCB.
SVF is a widely-adopted industry standard used to describe Joint Test Action Group (JTAG) signals in a more compact way than Standard Test and Programming Language (STAPL), making it more suitable in certain embedded programming applications.
The Nios Development Kit, based on the newest version of the Nios(R) embedded processor, includes evaluation versions of the Accelerated Technology (AT) code|lab Debug featuring Joint Test Action Group (JTAG) debug support.
The DMC provides access to the card's I/O during development, along with a Joint Test Action Group (JTAG)/Common On-chip Processor (COP) interface for application debug.

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