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The experimental task was programmed and performed on a Apple Macintosh II microcomputer with an MC68020 processor.
For the non-tiled histogram benchmark, array indexed loop executions times were 9% longer for the Spare, and 11% longer for the MC68020, than they are with pointer loops.
Tiled execution time of the histogram benchmark using array indexed loops is found to be 14% longer on the SPARC architecture, and 49% longer on the MC68020, than it is with pointer loops.
In the case of the MC68020 some benchmarks run faster when using variables, rather than constants, for the tile size parameters.
Histogram Sparc SS2 0:07 0:09 1.19 Sparc IPC 0:12 0:14 1.19 Sparc SS1 0:14 0:17 1.19 MC68020 0:31 0:43 1.42 I80386 0:39 0:58 1.47
Flight control is provided by a digital fly-by-wire avionics system directed by a central flight computer that uses an MC68020 microprocessor running the OS-9 real-time operating system on a 3U VME data bus.
This development concerns the realization of a state-of-the-art ESM processor running on a MC68020 32-bit microprocessor target.
Other interfaces to the host allow direct downloading to the target (MC68020).
There are believed to be few, if any, ESM processors written in Ada and executing on a MC68020 target.
This paper describes a recent, new development for MEL DSL in Canada on an Ada processor for an ESM system which runs on a MC68020 target microprocessor.
These provide fast computation via local MC68020 processors and detailed visual feedback through high-resolution color graphics images.
In the prototype, the data processor is implemented by the Motorola MC68020 central processing unit and the Motorola MC68881 floating point unit.