Often, these commercial tools are not available for a designer, but event-based logic simulators, such as ModelSim
, Active HDL, Xsim, Ghdl, Icarus, supporting either Verilog  or VHDL  are.
Quartus Prime 16.0 and ModelSim
6.2b is chosen as the synthesis and simulation tool.
Property description languages such as PSL or SVA are usually used for describing design properties and assertions which are simulated using simulation tools such as ModelSim
alongside the DUV.
Caption: Figure 4: ModelSim
functional testbench of the proposed system, with a comparison window length of J = 5.
The verilog code for the proposed system was simulated and successfully verified using ModelSim
6.4a and Xilinx 14.1 ISE.
To test the design and implementation of section (VI), two steps are carried out: - one for simulating SPIMN, as such, using ModelSim
ISE6.0, and the second is verifying it.
In our work, we use Mentor Graphic ModelSim
10.4d as the simulator.
Once the code is written, the HDL designer can use HDL Verifier to simulate the HDL design in the Simulink environment using ModelSim
, and compare the output of the HDL design to the output of the executable specification.
This latter can also create a testbench based on the vectors used in the Simulink specification and which can be run on Modelsim
or Xilinx ISE Simulator.