multiplier-accumulator

(redirected from Multiply-accumulate)
Also found in: Wikipedia.

multiplier-accumulator

A general-purpose floating point processor that multiplies and accumulates the results of the multiplication. Newer versions also perform division and square roots.
Copyright © 1981-2019 by The Computer Language Company Inc. All Rights reserved. THIS DEFINITION IS FOR PERSONAL USE ONLY. All other reproduction is strictly prohibited without permission from the publisher.
Mentioned in ?
References in periodicals archive ?
These are grouped into clusters, each of which contain 16 processing elements and additional compute units including two 32-bit MAC (multiply-accumulate) units that perform some of the key arithmetic functions in convolutional neural networks (CNNs).
INTRODUCTION Multiplication and multiply-accumulate operations are most frequently used blocks in digital signal processing [1][4].
DSP architecture accomplishes both through the use of single-instruction, multiple-data (SIMD) operations and high-efficiency multiply-accumulate operations.
== ARM == * QEMU now supports the new Cortex-A15 instructions in linux-user mode (via "-cpu any"): VFPv4 fused multiply-accumulate (VFMA, VFMS, VFNMA, VFNMS) and also integer division (UDIV, SDIV).
Using high-speed libraries, an IP block with 64 cores, 16 shared floating point and multiply-accumulate units, and without memory occupies less than 12mm2 (0.19 mm2/core).
In many signal-processing algorithms including filtering, multiply-accumulate operations are common.
LSI Logic's ZSP400 is a state-of-the-art, four-way superscalar, high-performance dual-MAC (multiply-accumulate) DSP developed in a fully synthesizable, five-stage pipeline design that is easily migrated to different manufacturing processes.
Other features include a single cycle 32x32 multiply-accumulate function to increase the speed and resolution of mathematical operations and extended addressing that supports up to 8Mb of program memory and up to 8Gb of data.
The SH7615 processor's hybrid RISC DSP has an extended Harvard Architecture which simultaneously accesses two data and one address bus and also can sustain a multiply-accumulate function in a single-clock cycle.
But application developers who wish to use the extended registers, memory management, and new instructions, such as the combined a*b+c=d multiply-accumulate floating point instruction, will have to start porting.
Since multiply-accumulate operations are at the heart of many DSP algorithms, MACS (multiply-accumulates per second) is another DSP performance measure.