NMOS


Also found in: Dictionary, Acronyms, Wikipedia.

NMOS

[′en‚mȯs]
(electronics)
Metal-oxide semiconductors that are made on p-type substrates, and whose active carriers are electrons that migrate between n-type source and drain contacts. Derived from n-channel metal-oxide semiconductor.
McGraw-Hill Dictionary of Scientific & Technical Terms, 6E, Copyright © 2003 by The McGraw-Hill Companies, Inc.

NMOS

(Negative-channel MOS) Pronounced "n-moss." A type of transistor used for logic and memory chips. NMOS transistors are faster than their PMOS counterpart, and more of them can be put on a single chip. NMOS is also used in CMOS design. For more details, see MOSFET.
Copyright © 1981-2019 by The Computer Language Company Inc. All Rights reserved. THIS DEFINITION IS FOR PERSONAL USE ONLY. All other reproduction is strictly prohibited without permission from the publisher.
References in periodicals archive ?
The pole frequency of the NMOS and PMOS shifters are measured as 9.4 MHz and 8.9 MHz for 5 pF floating capacitor.
In addition, in order to investigate the relationship between the energy of substrate hot carrier and gate voltage and substrate bias voltage, another two test cases are added in this study: (4) [V.sub.G] = 1.7 V and [V.sub.S] = -2 Vand (5) [V.sub.G] = 1.2 V and [V.sub.S] = -2.5 V on the 2 nm thick oxide NMOS capacitors.
In countries like the United States, where existing media subsidies are insufficient, the NMO model could also provide a novel and extremely efficient way for the government to increase its contribution to the health of the media.
The old logical state is preserved on a capacitive load until the information slope opens the NMOS transistor and pulls the output node no to logical low.
Obviously, the NMOS series configuration of the logic tree in dual-rail MCML circuits limits the reduction of the minimum supply voltage.
Both NMOS and PMOS sleep transistors connected between PUN and PDN are turned on and output is evaluated.
The buffer structure of the VCO use an open drain NMOS, which size is half of the cross coupled NMOS pair.
An NMOS protection structure which utilizes dynamic threshold MOS (DTMOS) concept is proposed in Figure 2(b) [10, 11].
L'Assemblee Generale L'Assemblee Generale (The General Assembly ou GA) est composee des representants de toutes les NMOs et se reunit deux fois par an, en Mars et en Aout (March Meeting et August Meeting).
As a world's first, Fujitsu Laboratories developed new technology for 32nm-generation LSIs that can be used with existing 45nm-generation fabrication facilities using a (110) silicon substrate to enable increase in PMOS on-current, with no drop in NMOS on-current, in comparison with a (001) surface.
The PA uses a diode connected NMOS transistor functioning as a diode linearizer.