Peripheral Component Interconnect

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peripheral component interconnect

[pə‚rif·ə·rəl kəm‚pō·nənt ′in·tər·‚kə·nek]
(computer science)
A bus standard for connecting additional input/output devices (such as graphics or modem cards) to a personal computer. Abbreviated PCI.
McGraw-Hill Dictionary of Scientific & Technical Terms, 6E, Copyright © 2003 by The McGraw-Hill Companies, Inc.

Peripheral Component Interconnect

(PCI) A standard for connecting peripherals to a personal computer, designed by Intel and released around Autumn 1993. PCI is supported by most major manufacturers including Apple Computer. It is technically far superior to VESA's local bus. It runs at 20 - 33 MHz and carries 32 bits at a time over a 124-pin connector or 64 bits over a 188-pin connector. An address is sent in one cycle followed by one word of data (or several in burst mode).

PCI is used in systems based on Pentium, Pentium Pro, AMD 5x86, AMD K5 and AMD K6 processors, in some DEC Alpha and PowerPC systems, and probably Cyrix 586 and Cyrix 686 systems. However, it is processor independent and so can work with other processor architectures as well.

Technically, PCI is not a bus but a bridge or mezzanine. It includes buffers to decouple the CPU from relatively slow peripherals and allow them to operate asynchronously.
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(1) (Payment Card Industry) See PCI DSS.

(2) (Peripheral Component Interconnect) A hardware interface for connecting peripheral devices to a computer. Introduced in 1993 and designed by Intel, Compaq and Digital Equipment, PCI superseded the ISA interface. PCI was widely used before it was superseded by PCI Express a decade later.

When first deployed, personal computers had several PCI slots; however, as time passed more computers used control circuits built into the motherboard chipsets, and the need for multiple slots diminished. Motherboards would later have only one PCI slot and an AGP slot for graphics. Eventually, PCI Express (PCIe) became the primary hardware interface for personal computers. See PCI Express and ISA.

PCI Made Life a Lot Easier
PCI eliminated conflicts that plagued the earlier ISA bus, which required an interrupt request (IRQ) number to be assigned to each ISA card. In contrast, the PCI bus architecture shares IRQs. Motherboards with both ISA and PCI were made for several years, and if there was only one IRQ left after the rest were assigned to ISA cards, all PCI devices could share it.

PCI Slots
PCI supports bus mastering, 32 and 64-bit data paths and runs at 33 or 66 MHz. The slot quantity is based on 10 electrical loads that deal with inductance and capacitance. The PCI chipset uses 3, motherboard controllers use 1, and plug-in cards use 1.5. For more slots, two PCI buses can be bridged. To compare data rates, see PCI-SIG. See bus mastering, PCI-X, Concurrent PCI, CompactPCI, PXI, PC data buses, PICMG and Sebring ring.

PCI Slots Are Not PCI Express (PCIe)
PCI sockets are not the same as PCIe. In addition, PCIe slots come in different sizes.

How PCI Is Connected
This illustration shows how the CPU, memory and peripherals are interconnected in a PC. Today's motherboards may not have any PCI slots. See PCI Express.
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References in periodicals archive ?
On the contrary, the PCI Bridge Design Manual [18] presents multipliers that can be easily used to predict long-term deformation of PSC bridges.
Binard for "UHPC: A Game-Changing Material for PCI Bridge Producers," in the March-April 2017 edition; and,
In the high-speed data acquisition and transmission applications, high-speed data exchange between the host and external devices can be achieved by realizing DMA data transfer using the PCI bridge chip.
"We would use one PCI bridge with multiple complex programmable logic devices (CPLDs) or FPGAs to implement the required timing and flexible settings and coordinate the analog I/O data transfer with the PCI bridge direct memory access (DMA) engines." He continued, "Now, with our investment in FPGA coding and our own IP, we significantly save cost, and with the improved functionality of today's FPGAs, we also integrate additional functions such as stepper motor control, encoder inputs, and pulse generators as well as digital I/O."
When the PCIe to PCI bridge was originally envisioned, it was in a forward-mode application--that is, for bridging a PCIe root complex to one or more PCI (or PCI-X) bus(es).
PureSpec models all devices in the PCI Express topology, including the root complex, switch, endpoint, and PCI Express to PCI bridge. Within PureSpec, all protocol layers -- physical, data link, transaction -- of the PCI Express specification are modeled and can be simulated concurrently or independently.
PureSpec models all devices in the PCI Express topology, including the root complex, switch, endpoint, and PCI Express to PCI bridge. Within PureSpec, all protocol layers (physical, data link, transaction) of the PCI Express specification are completely modeled and can be simulated concurrently or independently.
All three of the processor subcircuits are linked by a 66 MHz local PCI bus to a pair of PCI bridge devices, one for the local on-card disk and LAN I/O, and one for the 33 MHz system level PCI bus that spans multiple card slots in the chassis
The Centillium Optimizer also eliminates the need for a PCI bridge, an additional savings in this extremely cost-sensitive platform.
An optional Advanced PCI Bridge is available from Sun to expand the number of PCI devices supported to a total of 32 devices at 33 MHz.
-- Compatibility: The Zoran PCI bridge is a PCI bus master with video overlay built-in, speeding data and video transfers through the PC.
The card uses a 400K gate Spartan3 FPGA and a bus mastering PCI bridge for high performance.