PCI bus

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Since transactions on PCI bus are far faster than those on back-end bus [11], a FIFO or RAM block is necessary to serve as a buffer in order to balance the speed difference.
Considering efficiency, for example, a 33 MHz, 32-bit PCI bus requires 49 signal lines to deliver its 132 Mbytes/second, while a x1 PCI Express interface requires only 11 signals for its 250 Mbytes/second.
Available now, this new chip addresses current requirements because of a widespread transition in desktop PCs from PCI bus technology to alternative buses such as USB.
Since its inception in 1992, the PCI bus has become the I/O backbone of nearly every computing platform, and is the primary interface for desktop computers and peripheral cards.
Multiple DM642s can be seamlessly connected via the 66 MHz PCI bus interface for high-speed connectivity.
These peripherals share the computer's PCI bus - a "data highway" with a top speed of 133 megabytes per second (MB/s).
Standard 32-bit PCI bus expansion cards are not optimal for Gigabit Ethernet.
The frame grabber also provides real-time transfer over the PCI bus system memory for analysis.
The PrPMC communicates to the baseboard (also sometimes called a carrier card) through the industry-standard PCI bus running at up to 66 MHz and 64 bit wide bus or 528 MBytes/sec.
NEC Electronics' VRC5477 system controller is a software-configurable chip that directly connects the VR5500 CPU to synchronous dynamic random access memory (SDRAM) memory, a 32-bit PCI bus, and a local bus without external logic or buffering.
The Agilent E2930A Protocol Analyzer for PCI-X 2.0 is used to view traffic on the PCI bus and debug system performance through root-cause analysis and trouble-shooting.