PCI bus


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PCI bus

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PCI

(1) (Payment Card Industry) See PCI DSS.

(2) (Peripheral Component Interconnect) A hardware interface for connecting peripheral devices to a computer. Introduced in 1993 and designed by Intel, Compaq and Digital Equipment, PCI superseded the ISA interface. PCI was widely used before it was superseded by PCI Express a decade later.

When first deployed, personal computers had several PCI slots; however, as time passed more computers used control circuits built into the motherboard chipsets, and the need for multiple slots diminished. Motherboards would later have only one PCI slot and an AGP slot for graphics. Eventually, PCI Express (PCIe) became the primary hardware interface for personal computers. See PCI Express and ISA.

PCI Made Life a Lot Easier
PCI eliminated conflicts that plagued the earlier ISA bus, which required an interrupt request (IRQ) number to be assigned to each ISA card. In contrast, the PCI bus architecture shares IRQs. Motherboards with both ISA and PCI were made for several years, and if there was only one IRQ left after the rest were assigned to ISA cards, all PCI devices could share it.

PCI Slots
PCI supports bus mastering, 32 and 64-bit data paths and runs at 33 or 66 MHz. The slot quantity is based on 10 electrical loads that deal with inductance and capacitance. The PCI chipset uses 3, motherboard controllers use 1, and plug-in cards use 1.5. For more slots, two PCI buses can be bridged. To compare data rates, see PCI-SIG. See bus mastering, PCI-X, Concurrent PCI, CompactPCI, PXI, PC data buses, PICMG and Sebring ring.


PCI Slots Are Not PCI Express (PCIe)
PCI sockets are not the same as PCIe. In addition, PCIe slots come in different sizes.







How PCI Is Connected
This illustration shows how the CPU, memory and peripherals are interconnected in a PC. Today's motherboards may not have any PCI slots. See PCI Express.
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References in periodicals archive ?
Since transactions on PCI bus are far faster than those on back-end bus [11], a FIFO or RAM block is necessary to serve as a buffer in order to balance the speed difference.
Considering efficiency, for example, a 33 MHz, 32-bit PCI bus requires 49 signal lines to deliver its 132 Mbytes/second, while a x1 PCI Express interface requires only 11 signals for its 250 Mbytes/second.
Available now, this new chip addresses current requirements because of a widespread transition in desktop PCs from PCI bus technology to alternative buses such as USB.
Since its inception in 1992, the PCI bus has become the I/O backbone of nearly every computing platform, and is the primary interface for desktop computers and peripheral cards.
Multiple DM642s can be seamlessly connected via the 66 MHz PCI bus interface for high-speed connectivity.
These peripherals share the computer's PCI bus - a "data highway" with a top speed of 133 megabytes per second (MB/s).
Standard 32-bit PCI bus expansion cards are not optimal for Gigabit Ethernet.
The frame grabber also provides real-time transfer over the PCI bus system memory for analysis.
The PrPMC communicates to the baseboard (also sometimes called a carrier card) through the industry-standard PCI bus running at up to 66 MHz and 64 bit wide bus or 528 MBytes/sec.
NEC Electronics' VRC5477 system controller is a software-configurable chip that directly connects the VR5500 CPU to synchronous dynamic random access memory (SDRAM) memory, a 32-bit PCI bus, and a local bus without external logic or buffering.
The Agilent E2930A Protocol Analyzer for PCI-X 2.0 is used to view traffic on the PCI bus and debug system performance through root-cause analysis and trouble-shooting.