PLD


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PLD

Programmable Logic Device

PLD

(Programmable Logic Device) A variety of logic chips that are programmable at the customer's site, the customer being the vendor of the finished chip, not the end user. Programmability of logic means that new chip designs can be tested and easily changed without incurring the huge photomask costs for chips completed in a semiconductor fab. In addition, memory-based PLDs can be reprogrammed over and over, which allows working products to be upgraded at the user's site.

PLDs are prefabricated with different types of logic circuits (from a handful to hundreds of thousands), all waiting to be interconnected according to the customer's requirements. See ASIC, soft core and adaptive computing.

Programmable Once (Fusible Links and Antifuse)
Fuse-based PLDs are permanent "one-time programmable" (OTP) chips. "Fusible links" are programmed by electrically melting conductive aluminum traces (blowing microscopic fuses). "Antifuse" is the opposite. Instead of destroying conducting links, they are "grown" by sending charges into tiny blocks of insulating silicon that become conductive silicon.

Reprogrammable (Memory Based)
Reprogrammable PLDs store their logic design in an EPROM, EEPROM, flash or SRAM memory that associates each programmable connection point with a memory cell (is the connection open or closed). SRAM-based PLDs are reloaded at startup, making them dynamic and adaptive to new requirements on the spur of the moment.

SPLDs and CPLDs
Simple PLDs (SPLDs) are devices with an AND array feeding an OR array or something similar, the differences being whether one or both arrays are programmable. SPLDs are programmed via fusible link, antifuse, EPROM, EEPROM or flash. Complex PLDs (CPLDs) are formed from a number of SPLDs connected together by a programmable switching matrix. CPLDs are typically EEPROM, flash and SRAM based.

PLDs are always used for logical functions, and programmable storage chips such as PROMs and EPROMs are considered PLDs if they contain program code rather than just data.

FPGAs
Field programmable gate arrays are another major programmable logic technology that some vendors classify under the PLD umbrella while others keep them separate. In either case, both FPGAs and PLDs fall within the "field programmable device" (FPD) category (see FPGA).


The ASIC Family
PLDs fall under the most generic definition of application specific ICs (ASICs). (Diagram courtesy of Clive Maxfield, www.techbites.com)
References in periodicals archive ?
The PLD must develop an SOP to oversee quality control personnel to ensure that manufacturing, packaging, labeling, and holding operations guarantee the quality of its products and that its products are packaged and labeled in accordance with established specifications.
Tomorrow's PLD designers need to be accustomed to the tools they will be using, especially with the complexity and time-to-market constraints we already see in today's PLDs," said Anne Sanquini, vice president and general manager, HDL Design division, Mentor Graphics.
Many studies have used the mean PLD to assess the recruitment dynamics of T bifasciatum (2, 3, 4, 7, 8, 9).
Encuestas de opinion indicaron que las preferencias electorales del PLD, en visperas de los comicios para renovar la mitad del Senado, habian, caido al treinta por ciento.
The new process will generate no secondary materials, as 100% of the PLD process %waste% will be reused to feed the beneficiary%s sinter plant, where it will replace the primary raw material iron ore.
In addition, the 1208P1 device is equipped with on-chip programmable voltage references for supply monitoring, 4 noise-immune digital inputs and 4 open-drain digital outputs for system control interfacing, 4 programmable timers with an on-chip 1 MHz oscillator for delay control and a 16 macrocell Complex PLD (CPLD) to implement sequencing and control functions.
SAN FRANCISCO -- TriCN, a leading developer of intellectual property (IP) for high-speed semiconductor interface technology, and PLD Applications (PLDA), a leading developer of PCI IP Core solutions, today announced the interoperability of TriCN's PCI-Express PHY and the PLDA PCI-Express IP Core, providing customers with a complete validated PCI-Express(TM) solution.
Fitch anticipates that PLD will continue to dispose of its remaining cold storage assets.
And since Universal Scan is not vendor specific - it works on any part with a JTAG interface - it can be used on any FPGA, PLD, Microprocessor, DSP, ASIC, etc.