PLL


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PLL

(electronics)

PLL

PLL

(Phase-Locked Loop) An electronic circuit that compares an input frequency and phase to a reference signal. It then generates a voltage proportional to the difference between the input and the reference. PLLs are used in myriad digital and mixed mode (analog and digital) applications as regulators, demodulators, synchronizers and frequency multipliers and dividers. For example, in a superheterodyne FM radio, a PLL is used to lock the local oscillator to an accurate frequency reference such as a crystal or ceramic resonator. It can also be used to demodulate the FM audio and stereo subcarrier signals from the intermediate frequency (IF) stage. See heterodyning.


PLLs in an FM Radio
This example shows how PLLs are used for regulation and demodulation in an FM radio tuned to 101.5 MHz. The FM frequency range is 88-108 MHz, and this example uses a 10.7 MHz intermediate frequency (IF) and a 1 MHz reference frequency.
References in periodicals archive ?
PLL has continued to thrive for half a century due to the hard work and support of many.
General case of the time relation between an input signal Sin and an output signal Sop of PLL is shown in Fig.
In this work, we prepared PLL, agarose and PLL/agarose coatings on the standard glass slides as oligonucleotide microan-ay substrates.
The prototype PLL hardware that we developed in our laboratory is shown in Fig.
A study [12] evaluating CD11c+ CD5+ chronic B-cell leukemias found that these represent forms of either CLL or PLL rather than HCL.
PLL phase noise figure of merit: -223 dBc/Hz, an improvement of 3 dB improvement over the ADF4153
In recent years, the authorities have successfully reduced fiscal and external vulnerabilities and implemented key reforms with the support of two successive 24-month PLL arrangements.
PLL would like to welcome as its new editor Associate Professor Helena Gurfinkel.
This paper investigates a novel three-phase PLL which is capable of locking to the phase and frequency of three-phase ac supply voltage under distorted conditions, which is based on the conventional PLL structure followed by an adaptive notch filter (ANF)and proportional-integral (PI) controller.
Whenever the built-in Intelligent Dynamic Clock Switch (IDCS) detects a failure on one of the two clock inputs, it automatically switches the PLL reference clock to the other input while minimizing the output phase transient.
The 4352S includes a "carrier lack multi-mode PLL circuit", developed for high-speed phase noise measurements.