Ladhake, "Design of low power phase lock
loop using 45 nm VLSI technology," International Journal of VLSI Design & Communication Systems, vol.
* A GPS driven, mixed-signal phase lock
loop that provides a 1 PPS CMOS output.
Using TSMC's proprietary 65nm CyberShuttle prototyping service, the prestigious university in mainland China made breakthroughs in developing phase lock
loop and analog digital converter technologies.
Key features/specification: Soft, padded lightweight design, 863-865MHz radio frequency transmission, PLL (phase lock
loop) transmitter, auto tune, volume control built into headset and 12 month guarantee.
Also features a front-loading CD player with remote control, MW/FM/PLL (phase lock
loop) radio with 5 pre-sets for each band' back-lit display, 5 pre-set graphic equaliser for rock, jazz, classical etc.
It incorporates an NTSC/PAL video input port, integrated Analog-to-Digital Converter (ADC) with Phase Lock
Loop (PLL) and LVDS transmitters.
The TDA8260 integrated circuit combines in one chip the features of a zero-IF quadrature phase shift keyring/8PSK demodulator and a low-noise phase lock
loop frequency synthesiser, enabling a reduction in the PCB area.
Although the UPS would run from the engine generator, the UPS rarely could phase lock
synchronize to the engine generator and confirmed this with a constant "bypass not available" indication.
A high speed Clock and Data Recovery unit (CDR) uses sophisticated Phase Lock
Loop (PLL) techniques to monitor the edges of the incoming serial data and extract a recovered clock at the bit rate.
* A high Q frmdamental mode crystal and analog Phase Lock
Loop (PLL) multiplier for single or dual frequency.
Lucent Technologies has introduced the LCK 4953 Voltage Phase Lock
Loop Clock Driver, a clock driver chip targeted at high-end computer workstations and network servers.