phase-locked loop

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phase-locked loop

[′fāz ¦läkt ′lüp]
A circuit that consists essentially of a phase detector which compares the frequency of a voltage-controlled oscillator with that of an incoming carrier signal or reference-frequency generator; the output of the phase detector, after passing through a loop filter, is fed back to the voltage-controlled oscillator to keep it exactly in phase with the incoming or reference frequency. Abbreviated PLL.
McGraw-Hill Dictionary of Scientific & Technical Terms, 6E, Copyright © 2003 by The McGraw-Hill Companies, Inc.


(Phase-Locked Loop) An electronic circuit that compares an input frequency and phase to a reference signal. It then generates a voltage proportional to the difference between the input and the reference. PLLs are used in myriad digital and mixed mode (analog and digital) applications as regulators, demodulators, synchronizers and frequency multipliers and dividers. For example, in a superheterodyne FM radio, a PLL is used to lock the local oscillator to an accurate frequency reference such as a crystal or ceramic resonator. It can also be used to demodulate the FM audio and stereo subcarrier signals from the intermediate frequency (IF) stage. See heterodyning.

PLLs in an FM Radio
This example shows how PLLs are used for regulation and demodulation in an FM radio tuned to 101.5 MHz. The FM frequency range is 88-108 MHz, and this example uses a 10.7 MHz intermediate frequency (IF) and a 1 MHz reference frequency.
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References in periodicals archive ?
Carrier phase is tracked by the phase lock loop (PLL) in a conventional GNSS receiver.
A lowpower 24 GHz phase lock loop with gain-boosted charge pump embedded in 0.18 gm COMS technology, in 2012 Asia Pacific Microwave Conference Proceedings, 4-7 December 2012, Kaohsiung, Taiwan, 643-645.
Ladhake, "Design of low power phase lock loop using 45 nm VLSI technology," International Journal of VLSI Design & Communication Systems, vol.
* A GPS driven, mixed-signal phase lock loop that provides a 1 PPS CMOS output.
Using TSMC's proprietary 65nm CyberShuttle prototyping service, the prestigious university in mainland China made breakthroughs in developing phase lock loop and analog digital converter technologies.
The module is a GPS driven, mixed signal phase lock loop, providing a 1 PPS CMOS output and generating a 10 MHz CMOS and 10 MHz SINE output from an intrinsically low jitter voltage controlled crystal oscillator.
Key features/specification: Soft, padded lightweight design, 863-865MHz radio frequency transmission, PLL (phase lock loop) transmitter, auto tune, volume control built into headset and 12 month guarantee.
Also features a front-loading CD player with remote control, MW/FM/PLL (phase lock loop) radio with 5 pre-sets for each band' back-lit display, 5 pre-set graphic equaliser for rock, jazz, classical etc.
It incorporates an NTSC/PAL video input port, integrated Analog-to-Digital Converter (ADC) with Phase Lock Loop (PLL) and LVDS transmitters.
The success of these systems depends partly on the phase noise performance of the phase lock loop (PLL) synthesizer.
The TDA8260 integrated circuit combines in one chip the features of a zero-IF quadrature phase shift keyring/8PSK demodulator and a low-noise phase lock loop frequency synthesiser, enabling a reduction in the PCB area.
A high speed Clock and Data Recovery unit (CDR) uses sophisticated Phase Lock Loop (PLL) techniques to monitor the edges of the incoming serial data and extract a recovered clock at the bit rate.