phase-locked loop

(redirected from Phase lock loop)

phase-locked loop

[′fāz ¦läkt ′lüp]
(electronics)
A circuit that consists essentially of a phase detector which compares the frequency of a voltage-controlled oscillator with that of an incoming carrier signal or reference-frequency generator; the output of the phase detector, after passing through a loop filter, is fed back to the voltage-controlled oscillator to keep it exactly in phase with the incoming or reference frequency. Abbreviated PLL.
References in periodicals archive ?
Using TSMC's proprietary 65nm CyberShuttle prototyping service, the prestigious university in mainland China made breakthroughs in developing phase lock loop and analog digital converter technologies.
It incorporates an NTSC/PAL video input port, integrated Analog-to-Digital Converter (ADC) with Phase Lock Loop (PLL) and LVDS transmitters.
A digital phase lock loop (DPLL) is included on each port, and the board supports data rates up to 128K bps in burst mode.
PHOENIX -- NB4N507A integrated Phase Lock Loop (PLL) is a cost-effective, configurable precision timing solution for a wide variety of consumer and networking applications
com) today announced that it has delivered to customers the industry's first register and Phase Lock Loop (PLL) for registered DIMMs (RDIMM) operating at 667 and 800 Mbps using Double Data Rate2 (DDR2) technology.
The M28950 provides a dedicated Z-bit signaling interface that, together with the integrated digital phase lock loop (DPLL) and slip buffer, provides a glue-less interface to widely-used CODECs and ISDN devices.
To address that market, Innovative has developed several mixed-signal blocks including USB, IEEE-1394 PHY, Phase Lock Loop (PLL), Clock and Data Recovery (CDR).
have announced a licensing agreement that lets system-on-chip (SoC) designers access essential Parthus phase lock loop (PLL) intellectual property (IP) from 1st Silicon as part of the Company's foundry service.
Peregrine Semiconductor, an innovative supplier of high-performance integrated circuits for the optical networking and wireless communications markets, today announced the first two products of a new family of high performance Phase Lock Loop (PLL) synthesizers with embedded EEPROM memory, ideal for fixed frequency applications.
TCXOs with digital compensation are available at similar stabilities, but are inherently noisy and exhibit discrete steps in frequency as the compensation data is updated causing loss of lock in phase lock loop applications, disrupting system timing integrity.
It includes digital scan tuning with phase lock loop technology which enables the 2ner to aggressively search for stations and lock on with virtually no drift, thus no static from an out of tune station.
The local oscillator structure is formed around a fractional-N phase lock loop (PLL) with all components integrated, save for the external passive loop filter.