phase-locked loop

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phase-locked loop

[′fāz ¦läkt ′lüp]
(electronics)
A circuit that consists essentially of a phase detector which compares the frequency of a voltage-controlled oscillator with that of an incoming carrier signal or reference-frequency generator; the output of the phase detector, after passing through a loop filter, is fed back to the voltage-controlled oscillator to keep it exactly in phase with the incoming or reference frequency. Abbreviated PLL.
McGraw-Hill Dictionary of Scientific & Technical Terms, 6E, Copyright © 2003 by The McGraw-Hill Companies, Inc.

PLL

(Phase-Locked Loop) An electronic circuit that compares an input frequency and phase to a reference signal. It then generates a voltage proportional to the difference between the input and the reference. PLLs are used in myriad digital and mixed mode (analog and digital) applications as regulators, demodulators, synchronizers and frequency multipliers and dividers. For example, in a superheterodyne FM radio, a PLL is used to lock the local oscillator to an accurate frequency reference such as a crystal or ceramic resonator. It can also be used to demodulate the FM audio and stereo subcarrier signals from the intermediate frequency (IF) stage. See heterodyning.


PLLs in an FM Radio
This example shows how PLLs are used for regulation and demodulation in an FM radio tuned to 101.5 MHz. The FM frequency range is 88-108 MHz, and this example uses a 10.7 MHz intermediate frequency (IF) and a 1 MHz reference frequency.
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References in periodicals archive ?
Zhu, "Analysis of period jitter induced by power supply noise of phase locked loop," Electronic Science and Technology, vol.
Gu, "Phase locked loop and simulation methods for grid interfaced converters", A Review, in Electrical Review, no.
The CVSS-945 is appropriate in PLL (phase locked loop) applications where the requirement is translating from 10 MHz to 100 MHz, for example.
The MMIC VCOs contain the resonator structure, negative resistance circuitry, tuning varactor, a frequency divider to feed the phase locked loop (PLL) and an output buffer amplifier.
Mitel Corp's Mitel Semiconductor division has launched three new 3.3-volt digital phase locked loop (PLL) chips for regulating the timing function in central office and customer premises equipment.
It features low power, high sensitivity (-100 dBm at 250 kbps, -92 dBm at 2 Mbps), data rates from 250 kbps up to 2 Mbps, and integrates a digital RSSI (received signal strength indictor), realtime-clock (RTC) and programmable clock output, a Gaussian filter, PIX (phase locked loop) and loop filter.
The basic form of a phase locked loop (PLL) consists of a voltage controlled oscillator (VCO), a phase detector (PD), and a filter.
The ADF42xx family of dual phase locked loop (PLL) synthesizers deliver outstanding phase noise performance for frequency and timing generation applications.
The model PLL500-915 phase locked loop (PLL) generates frequencies from 902 to 928 MHz in 200 kHz steps.
The TCXO can be disabled for high stability, set to around [+ or -]5 ppm for simple aging adjustment, specified to over [+ or -]32 ppm for Stratum 4 phase locked loop applications, or any option in between.
Features include embedded 10/100 Mbps Ethernet PHY and MAC, compliant with the IEEE 802.3 specification; dedicated, deeply embedded digital signal processor (DSP) functionality to facilitate rapid operation of the PHY transceiver; 64 Kb of third-generation flash; a high-performance 25 MHz HCS12 core; a 10-bit, eight-channel analog-to-digital converter; a clock generation module with a phase locked loop; a four-channel 16-bit timer; two serial communication interfaces (SCIs) and a serial peripheral interface running at speeds up to 6.25 Mbps and an inter IC bus; and 8 Kb of static RAM.
The device is said to achieve jitter performance of less than 3 ps rms 10 Hz to 80 MHz by avoiding the use of of a phase locked loop in favor of a low-phase noise HFF (high-frequency fundamental) crystal and harmonic multiplication.