The performance of the phase-lock loop
is below this level.
intellectual property essential in designs and foundry
This family of high-performance, low-skew, low-jitter phase-lock loop
(PLL) clock drivers strengthens and extends IDT's already expansive product portfolio.
Externally adjustable loop filters allow for adjustment of the phase-lock loop
(PLL) bandwidths to compensate for reference clock noise.
The SCC also provides a programmable baud rate generator and digital phase-lock loop
(DPLL) for recovering data clocking from received data streams.
Features of the NP2510 include an integrated phase-lock loop
(PLL) based clock generator, a clock and data recovery (CDR) unit and a 16-bit 155 MHz parallel interface that can be operated in the LVPECL (Low Voltage Positive Emitter Coupled Logic).
Among the LCD controllers' most noteworthy technical features are its acceptance of both analog and digital inputs, IQScaling(tm) proprietary scaling engine, PerfectColor(tm) proprietary dithering algorithm, IQSync2(tm) advanced phase adjustment algorithm, integrated triple A/D converter and line-lock phase-lock loop
(PLL), and compliance with the Digital Video Interface (DVI) standard.
It has an on-chip phase-lock loop
(PLL) based clock generator, a clock and data recovery (CDR) unit and a 16-bit 155 MHz parallel interface that can be operated in the LVPECL (Low Voltage Positive Emitter Coupled Logic) or CMOS mode.
A typical example of a circuit where jitter measurements are important is a phase-lock loop
Both boards use Sony's CXA3256R analog-to-digital converter (ADC) integrated circuit (IC) and Sony's CXA3106Q phase-lock loop
Both chips utilize ICS's phase-lock loop
(PLL) clock synthesis circuitry, with the lowest measured jitter in the industry and a zero ppm (parts per million) synthesis error in the output frequencies.