phase-locked loop


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phase-locked loop

[′fāz ¦läkt ′lüp]
(electronics)
A circuit that consists essentially of a phase detector which compares the frequency of a voltage-controlled oscillator with that of an incoming carrier signal or reference-frequency generator; the output of the phase detector, after passing through a loop filter, is fed back to the voltage-controlled oscillator to keep it exactly in phase with the incoming or reference frequency. Abbreviated PLL.
References in periodicals archive ?
A 0.7-to-3.5 GHz 0.6-to-2.8 mW highly digital phase-locked loop with bandwidth tracking, IEEE Journal of Solid-State Circuits 46(8): 1870-1880.
For monocomponent AM-FM signals many successful demodulation approaches have existed, ranging from standard methods such as Hilbert transform demodulation [1] or phase-locked loops (PLL's) to the recent energy separation algorithm (ESA) that tracks and demodulates the energy of the source producing the AM-FM signal using instantaneous nonlinear differential operators [2]-[18].
The Modeling for All-Digital Phase-Locked Loop. Figure 1(a) shows the phase domain model of a second-order analogy PLL.
The important part of the phase-locked loop (PLL) is phase detector.
"At the other end of the frequency spectrum, this same 3.3 Volt VCXO easily handles phase-locked loop applications right up to 125 MHz."
In some cases, the use of crystal filters or phase-locked loops can be used to reduce the noise.
In this way, the phase of the bit synchronized clock can be changed and adjusted constantly in the phase-locked loop until the accurate synchronization signal is obtained [3].
In light of major ongoing restructuring in the power system and the proliferation of new devices, Karimi-Ghartemani summarizes his experience from working with different phase-locked loop structures for power and energy applications.
The LM48903 stereo Class D spatial-array IC integrates a spatial processing DSP, two Class D amplifiers, 18-bit stereo analog-to-digital converter (ADC), phase-locked loop (PLL), and [I.sup.2]S and [I.sup.2]C interfaces.
TSMC's 28nm reference phase-locked loop (PLL) design was used to validate Synopsys' comprehensive custom solution while demonstrating productivity-enhancing capabilities of the TSMC AMS Reference Flow 1.0.
The reference signal generated by a phase-locked loop (PLL) affects the performance of custom power devices for compensating power factor, harmonic current, and voltage disturbances.
* An integrated phase-locked loop (PLL) and voltage-controlled oscillator (VCO) that performs clock conditioning.

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