Reduced Instruction Set Computer

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Related to Reduced Instruction Set Computer: complex instruction set computer

reduced instruction set computer

[ri¦düst in′strək·shən ‚set kəm′pyüd·ər]
(computer science)
A computer in which the compiler and hardware are interlocked, and the compiler takes over some of the hardware functions of conventional computers and translates high-level-language programs directly into low-level machine code. Abbreviated RISC.
McGraw-Hill Dictionary of Scientific & Technical Terms, 6E, Copyright © 2003 by The McGraw-Hill Companies, Inc.

Reduced Instruction Set Computer

(RISC) A processor whose design is based on the rapid execution of a sequence of simple instructions rather than on the provision of a large variety of complex instructions (as in a Complex Instruction Set Computer).

Features which are generally found in RISC designs are uniform instruction encoding (e.g. the op-code is always in the same bit positions in each instruction which is always one word long), which allows faster decoding; a homogenous register set, allowing any register to be used in any context and simplifying compiler design; and simple addressing modes with more complex modes replaced by sequences of simple arithmetic instructions.

Examples of (more or less) RISC processors are the Berkeley RISC, HP-PA, Clipper, i960, AMD 29000, MIPS R2000 and DEC Alpha. IBM's first RISC computer was the RT/PC (IBM 801), they now produce the RISC-based RISC System/6000 and SP/2 lines.

Despite Apple Computer's bogus claims for their PowerPC-based Macintoshes, the first RISC processor used in a personal computer was the Advanced RISC Machine (ARM) used in the Acorn Archimedes.
This article is provided by FOLDOC - Free Online Dictionary of Computing (
References in periodicals archive ?
The following comments are taken from the discussion of Complex Instruction Set Computers and Reduced Instruction Set Computers appearing in The Winn L.
To keep their information fresh, ASFSA used an IBM computer with Reduced Instruction Set Computer (RISC) architecture.
Battenfeld claims that transputers are distinguished from typical multiprocessor control systems in two ways: First, transputers are based on RISC (reduced instruction set computer) architecture, which makes possible rapid processing and simultaneous handling of multiple tasks.

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