scan design

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scan design

(Or "Scan-In, Scan-Out") A electronic circuit design technique which aims to increase the controllability and observability of a digital logic circuit by incorporating special "scan registers" into the circuit so that they form a scan path.

Some of the more common types of scan design include the multiplexed register designs and level-sensitive scan design (LSSD) used extensively by IBM. Boundary scan can be used alone or in combination with either of the above techniques.

["Digital Systems Testing and Testable Design" by Abramovici, Breuer, and Friedman, ISBN 0-7167-8179-4].

["Design of Testable Logic Circuits" by R.G. Bennetts, (Brunel/Southhampton Universities), ISBN 0-201-14403-4].
References in periodicals archive ?
Case studies analyze a DDR loopback test failure encountered on a map ball grid array packaged device, Zynq system-on-chip cache failure, single metal contact open induced scan chain failure, and signal corruption in scan chain.
Therefore, if a circuit has a mix of D-FFs and n-NOR cells, the n-NOR cells must be part of a separate scan chain. The procedure to scan-in a stream of bits into a scan chain consisting of n-NORs is as follows.
XJTAG Chain Checker identifies common errors in a JTAG scan chain, such as incorrectly connected and terminated test access ports (TAPs), and reports them to the developer.
In the event of unstable boundary scan chain test e.g., fan-out issues in long chains--use buffers at the TAP signals (TCK, TMS & TRST) to eliminate fan-out issues.
FIGURE 4 shows a boundary scan chain consisting of Ul, U2 and U5 boundary scan devices.
Data can be shifted into and out of the scan chain connecting the boundary scan cells on multiple devices on a board.
Disables output pins of all boundary scan devices in a boundary scan chain.
If the scan chain doesn't work properly, a common debug methodology is to reach for an oscilloscope to assess physical layer characteristics.
Connection tests focus on one device at a time, with other boundary scan chain devices used to support the target device test.
With the adoption of a two-wire interface on IEEE 1149.7, devices on the IEEE 1149.1 standard will benefit from this, as it makes it easier for boundary scan to be implemented on complicated new package technologies such as SoC, SoP and PoP, which does not implement 1149.1 boundary scan chain using the standard four or five-wire TAP interface.
These cells can be programmed via the JTAG scan chain to drive a signal onto a pin and across an individual trace on the board.