scan design

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scan design

(electronics)
(Or "Scan-In, Scan-Out") A electronic circuit design technique which aims to increase the controllability and observability of a digital logic circuit by incorporating special "scan registers" into the circuit so that they form a scan path.

Some of the more common types of scan design include the multiplexed register designs and level-sensitive scan design (LSSD) used extensively by IBM. Boundary scan can be used alone or in combination with either of the above techniques.

["Digital Systems Testing and Testable Design" by Abramovici, Breuer, and Friedman, ISBN 0-7167-8179-4].

["Design of Testable Logic Circuits" by R.G. Bennetts, (Brunel/Southhampton Universities), ISBN 0-201-14403-4].
References in periodicals archive ?
FIGURE 4 shows a boundary scan chain consisting of Ul, U2 and U5 boundary scan devices.
Data can be shifted into and out of the scan chain connecting the boundary scan cells on multiple devices on a board.
Disables output pins of all boundary scan devices in a boundary scan chain.
Connection tests focus on one device at a time, with other boundary scan chain devices used to support the target device test.
To fully test TSV connections, the Tessent SoCScan and Tessent FastScan[TM] products work together to use scan chain test patterns on one die to provide stimuli and capture results from another die, thereby testing the integrity of interface logic and TSV connections.
DFT MAX power optimization minimizes the number of scan chain connections that cross voltage domains, lowering the area impact of DFT by reducing the number of required level shifters and power isolation cells.
These cells can be programmed via the JTAG scan chain to drive a signal onto a pin and across an individual trace on the board.
Boundary Scan chain Checker and a BSCAN Chain debug wizard tool 2.
Synopsys Dedicates Scan Chain Inventions to Public Domain