Slot 1


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Slot 1

(hardware, standard)
The physical and electrical specification for the connector used by some of Intel's microprocessor cards, currently (August 1999) the SEPP Celeron and the SECC Pentium II.

Slot 1 is a departure from the square ZIF PGA/SPGA sockets used by Pentium and earlier processors, the processor being mounted on a card, with a 242-lead edge-connector.

The Slot 1 specification allows for higher bus rates than Socket 7. Slot 1 motherboards use the GTL+ bus protocol.

See also Slot 2, Slot A.

Slot 1

A 242-pin slot on the motherboard that holds Intel CPU modules including the Intel Single Edge Contact Cartridge (SECC and SECC2) and Single Edge Processor Package (SEPP). The Pentium II was the first to use Slot 1. Slot 1 is a narrow slot like a PCI bus slot, not a small rectangular chip socket. See Slot 2, SECC and Slot A.


Slot 1 and Socket 370
This motherboard supports both Slot 1 and Socket 370 for Pentium III chips.
References in periodicals archive ?
As per the telecom body, when a 4G only SIM is placed in the second SIM slot of a MediaTek enabled dual-SIM smartphone, it drastically reduced the data speeds from any SIM present in slot 1. As per COAI, there is almost 40% data drain from the SIM present in slot 1 of MediaTek powered dual-SIM devices.
To put this test we used a Lava Z25 dual-SIM smartphone with a Vodafone SIM in slot 1 and a Reliance Jio SIM in slot 2 of the device, given that Reliance Jio is the sole 4G-only SIM available in India for now.
SIM 2, we conducted another speedtest on the Vodafone SIM, which remained in SIM slot 1. The second speedtest showed a considerable decrease in download speeds, a 60% drop to be exact.
The optimal values from slot 1 to slot 4 are as follows: slot length = 4.65, 4.65, 4.65, and 4.57 (mm) and inclined angle = 20.5, 20.5, 20.5, and 20.5 (degree).
Designed to meet VITA 65, the versatile new backplane is extremely useful in environments that require various slot-to-slot optical or RF interconnects or that require optical or RF I/O together with a high speed data plane connection to slot 1.
Slot 1 is designed for a conventional 3U VPX module and has dedicated Fat Pipe connections to both slots 2 and 3.
Therefore, s2 immediately claims slot (i.e., slot 1) for transmitting data and lists this slot in its TL after finishing the cooperation between si and s2.
As si is the parent of s2, it records slot 1 in its RL, whereas s3 and s4 list slot 1 in their ULs as shown in Figure 4.
Note that node s6 can reuse slot 1 because slot 1 does is not used by its two-hop neighbors.
Slot 1 is dedicated to the system controller, embedded or external, using a PXI bus expander.
As shown in the figure, the available slot set of node x is [A.sub.x] = {1,3, 5} after the node x listens a cycle; node x occupies the slot 1 behind the slot 2 occupied by y, which is the nearest node behind x.