superscalar architecture


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superscalar architecture

[¦sü·pər‚skā·lər ′är·kə‚tek·chər]
(computer science)
A design that enables a central processing unit to send several instructions to different execution units simultaneously, allowing it to execute several instructions in each clock cycle.
References in periodicals archive ?
an 8K cache in the 486; 3) it has a much faster math co-processor unit than the 486; 4) it has superscalar architecture (more than one operation per clock tick); and 5) it has improved data corruption checking.
Superscalar architecture concepts have been described in detail in [2].
It has a 64-bit data path, a 16K internal cache, a much faster math coprocessor unit than the 486, superscalar architecture (more than one operation per clock tick), and improved data corruption checking.
In order for users to receive the best possible results from the superscalar architecture of the Pentium, software companies must recompile their applications.
The Pentium has a 64-bit data path, a larger internal cache (16K) and a faster math coprocessor than the 486, superscalar architecture (more than one operation per clock tick), and improved data corruption checking.
Among specific topics are the representation of information, inputs and outputs, virtual memory, caches in a multiprocessor environment, and superscalar architectures.
In order to overcome this limitation and better utilize the machine's available resources, most existing modern superscalar architectures are capable of searching and sending the ready instructions for execution beyond the stalling instruction (out-of-order execution).
These machines are pipelined superscalar architectures and the detection of parallelism is done by the hardware and so they are able to execute existing binaries.
The architecture allows us to achieve the performance advantages of simultaneous multithreading, while keeping intact the design and single-thread peak performance of the dynamically scheduled CPU core present in modern superscalar architectures.