systolic array


Also found in: Wikipedia.

systolic array

[si′stäl·ik ə′rā]
(computer science)
An array of processing elements of cells connected to a memory which pulses data through the array in such a way that each data item can be used effectively at each cell it passes while being pumped from cell to cell along the array.

systolic array

(architecture, parallel)
(By analogy with the regular pumping of blood by the heart) An arrangement of processors in an array (often rectangular) where data flows synchronously across the array between neighbours, usually with different data flowing in different directions. H. T. Kung and Charles Leiserson publish the first paper describing systolic arrays in 1978 Each processor at each step takes in data from one or more neighbours (e.g. North and West), processes it and, in the next step, outputs results in the opposite direction (South and East).

An example of a systolic algorithm might be matrix multiplication. One matrix is fed in a row at a time from the top of the array and is passed down the array, the other matrix is fed in a column at a time from the left hand side of the array and passes from left to right. Dummy values are then passed in until each processor has seen one whole row and one whole column. At this point, the result of the multiplication is stored in the array and can now be output a row or a column at a time, flowing down or accross the array.

See also Ruby, SISAL.

systolic array

An array of processing elements (typically multiplier-accumulator chips) in a pipeline structure that is used for applications such as image and signal processing and fluid dynamics. The "systolic," coined by H. T. Kung of Carnegie-Mellon, refers to the rhythmic transfer of data through the pipeline, like blood flowing through the vascular system.
Mentioned in ?
References in periodicals archive ?
Thus, the use of regular and modular computational structures as cycle convolution and circular correlation having local and regular data communications can be very useful in obtaining a good VLSI implementation for DCT, IDCT [10-18], DST and IDST [20-23], discrete Fourier transform (DFT) [12] or discrete Hartley transform (DHT) [24-29] using both the systolic array architectural paradigm or distributed arithmetic [30-34].
Thus the QRS detector has to undergo numerous computations to arrive at the output and a logical hierarchy from adder, systolic array, and filters and then to the peak detectors can be developed.
This paper proposes an FPGA based scalable systolic array architecture for QR decomposition based on Givens rotation algorithm using the concept of LUT based Newton-Raphson method for inverse square root and square root and achieves scalability using DPR.
The PEs are arranged in a systolic array to form the basis for the compute core, as demonstrated in Figure 4.
A systolic array is an arrangement of processors in an array where data flows synchronously between neighbors across the array, usually with different data flowing in different directions.
[7] Jingming Wang and Babak Daneshrad, A universal systolic array for linear MIMO detection.
The components denoted by [R.sup.-1](n) and a(n) can be efficiently computed by a triangular systolic array based on the Householder transformation.
Ingredients are propagated through a large 3-D lattice using vectorized pipeline SIMD parallel processing in a systolic array architecture that we call the Jell-O Engine.
In order to synthesize 1D systolic array (SA) that implements the computation defined by (1), it is enough to consider one iteration step only.
In (8), MM is implemented using systolic arrays for all-one polynomials and trinomials.
(IEEE Computer, January 1982) and among others we have On the Design of Algorithms for VLSI Systolic Arrays, D.