today announced the successful tape-out of a broad portfolio of DesignWare Foundation and Interface PHY IP for TSMC's 7-nm process technology, including logic libraries, embedded memories, embedded test and repair, USB 3.
Mentor, a Siemens business, today announced a new integration with PhoeniX Software that reduces tape-out time for integrated photonics designers by enabling faster iterations between final sign-off verification and the design tool.
Samsung Foundry has certified the Calibre YieldEnhancer product and specifically its SmartFill and ECO/Timing-Aware Fill capabilities to help designers make multiple design changes and still comply with manufacturing planarity requirements and tape-out schedules.
Mutual ARM and TSMC silicon partners have also benefitted from early access to ARM Artisan physical IP and 16nm FinFET+ tape-outs of the Cortex-A72 processor, the high- performance processor powering many of today's best-selling primary compute devices.
It supports the Linux platform, a significant extension of the AWR intelligent Net[TM] (iNet) technology to handle arbitrary layout geometries; automatic and "on the fly" connectivity extraction in layout; support for Verilog-A analog behavioral language; integration of an additional SPICE circuit simulator and electromagnetic (EM) simulators; and support for industry standard physical verification flow for final chip tape-outs.
Building on the earlier certification this year for TSMC's 7-nm process technology, the Synopsys Design Platform has been utilized extensively in multiple production tape-outs across wide-ranging market, including high-performance computing (HPC) and mobile.