Translation Look-aside Buffer

Translation Look-aside Buffer

(storage, architecture)
(TLB) A table used in a virtual memory system, that lists the physical address page number associated with each virtual address page number. A TLB is used in conjunction with a cache whose tags are based on virtual addresses. The virtual address is presented simultaneously to the TLB and to the cache so that cache access and the virtual-to-physical address translation can proceed in parallel (the translation is done "on the side"). If the requested address is not cached then the physical address is used to locate the data in main memory. The alternative would be to place the translation table between the cache and main memory so that it will only be activated once there was a cache miss.
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The AMD Athlon MP processor features the patented QuantiSpeed architecture, which includes a high performance full-speed cache with hardware data pre-fetch, a fully pipelined superscalar floating point engine, and an exclusive L2 Translation Look-aside Buffer (TLB).
The AMD Athlon MP processor features the patented QuantiSpeed(TM) architecture, which includes a high performance full-speed cache with hardware data pre-fetch, a fully pipelined superscalar floating point engine, and an exclusive L2 Translation Look-aside Buffer (TLB).
The AMD Athlon MP processor features the patented QuantiSpeed architecture, which includes a high performance full-speed cache with hardware data pre-fetch, a fully pipelined super scalar floating point engine, and an exclusive L2 Translation Look-aside Buffer (TLB).
The AMD Athlon MP processor features the patented QuantiSpeed(TM) architecture, which includes a high-performance full-speed cache with hardware data pre-fetch, a fully pipelined superscalar floating point engine, and an exclusive L2 Translation Look-aside Buffer (TLB).
The new AMD Athlon MP processor features the patented QuantiSpeed architecture, which includes a high performance full-speed cache with hardware data pre-fetch, a fully pipelined superscalar floating point engine, and an exclusive L2 Translation Look-aside Buffer (TLB).
The AMD Athlon MP processor, with stable Socket A infrastructure and support for DDR memory technology, has a high performance full-speed cache with hardware data pre-fetch, a fully pipelined superscalar floating point engine, and an exclusive L2 Translation Look-aside Buffer (TLB).
The new AMD Athlon MP processor features the patented QuantiSpeed(TM) architecture, which includes a high performance full-speed cache with hardware data pre-fetch, a fully pipelined superscalar floating point engine, and an exclusive L2 Translation Look-aside Buffer (TLB).
For faster translation of addresses, the 603 provides two four-entry, fully associative block address translation registers, and two 64-entry, 2-way set associative translation look-aside buffers (TLBs) for instructions and data.
The mobile AMD Athlon XP processor features QuantiSpeed architecture, which incorporates a nine-issue, fully pipelined superscalar microarchitecture, a superscalar floating point unit, hardware data pre-fetch, and exclusive and speculative Translation Look-aside Buffers (TLB).
The mobile AMD Athlon XP processor features QuantiSpeed architecture, which incorporates a nine-issue, fully pipelined superscalar micro-architecture, a superscalar floating-point unit, hardware data pre-fetch, and exclusive and speculative Translation Look-aside Buffers (TLB).

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