Resulting, using transmission gate in EBC and TG enjoys the least power, delay, and PDP as a complete part that does not need any mechanisms.
The transmission gate is made up of two field effect transistors thus the transistors are n-channel MOSFET and p-channel MOSFET are connected with parallel with each other.
The CMOS transmission gate consists of two MOSFETs, one n-channel responsible for correct transmission of logic zeros, and one p-channel, responsible for correct transmission of logic ones .
The power dissipation of CMOS circuit, pass transistors and transmission gate is 0.
The first device is a solid-state transmission gate
(t-gate) multiplexer that uses CNT as a channel in the Field Effect Transistors (FET) of both n-FET and p-FET types that are used.
For multiplexers and AND gates using the TSMC library executions while for the XOR gate we have used the faster ten transistor implementation based on transmission gate
XOR to tie the delay with AND gates.
The next design is Transmission Gate
Adder (TGA) .
Combinational Circuits Using Transmission Gate
Logic for Power Optimization.
is a good non mechanical relay also known as analog gate or analogue switch or electronic relay is built with CMOS technology.
Standard static complementary metal oxide semiconductor (CMOS), dynamic CMOS logic, complementary pass transistor logic (CPL)  and transmission gate
full adder (TGA) ,  are the most important logic design styles in the conventional domain.