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A Hardware Description Language for electronic design and gate level simulation by Cadence Design Systems.

xnf2ver is an XNF to Verilog translator.

["The Verilog Hardware Description Language", Donald E. Thomas & Philip Moorby, Kluwer, 1991].
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An HDL (hardware description language) used to design electronic systems at the component, board and system level. Developed by Phil Morby at Gateway Design Automation, it was introduced in 1985 along with Verilog-XL, a logic simulator.

By the late 1980s, Verilog was the de facto standard for proprietary HDLs. After Cadence Design Automation acquired it in 1989 and put it into the public domain in 1990, it became the IEEE 1364 standard in 1995 (Verilog 95).

SystemVerilog is an enhanced version of Verilog developed by Accellera (, an industry organization formed in 2000 by the consolidation of Open Verilog International (OVI) and VHDL International. Verilog and VHDL are the two major HDLs. See VHDL and RTL.

HDL Languages
Verilog and VHDL are the most popular HDLs. These examples show a circuit described in RTL in both languages and the resulting schematic of the gate level netlist created after synthesis (below). (Language and schematic examples from "HDL Chip Design" courtesy of Douglas J. Smith.)

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References in periodicals archive ?
Before, you would have to think about a very specific application and work really hard on developing the model and the firmware for either VHDL or Verilog. Now, you can think more broadly about how we can improve the physics, whether it's low-level aggregation of hits in some calorimeter all the way up to taking the full event and optimising for a particular topology.
The prioritization scheme and the MPRA architecture for 4 and 8 tasks were implemented and analyzed on Cyclone V, including: the adaptation and the implementation in Verilog code of the basic elements of the CPU (control unit, data memory and instruction memory, hazard detection unit, forward units, ALU, multiplexers); the Verilog code for the structures with the multiplied and multiplexed specific nMPRA resources: the PC register, the pipeline registers, the Register File and any other memory element.
Hakhamaneshi, "A Hardaware Implementation of The Advanced Encryption Standard (AES) Algorithm Using System Verilog, " Islamic Azad University, Iran, 2009.
A Verilog test fixture code which initializes and maintains the reset and clock signals is executed in ISim simulator which is embedded inside Xilinx ISE.
For building the chip from the Verilog code, the first step is to convert the behavioral level code to a netlist or gate level code.
In this project the coding was done using the Verilog HDL and software used is Xilinx ISE 14.7 provided by Xilinx.
Both the existing and proposed architectures are designed using Verilog HDL and developed in gate level for synthesis, using the Synopsys Design Compiler (DC) EDA tool.
SystemVerilog has combined many of the best features of both VHDL and Verilog.
The improved DDA algorithm is rewritten in Verilog HDL, and embedded in an FPGA device on board.
It was found that the Balsa system does not generate synthesized Verilog files for circuit specification codes 1-of-4 containing table definitions; in this case only the circuits with dual-rail encoding were implemented because of the SubWord function, which is part of both circuits of key generation, including tables to implement the Sbox for byte substitution.
frobas works closely with design and verification departments of their global customers, focusing on RTL design and functional verification based on SystemVerilog, Verilog, VHDL and SpyGlass CDC.
VHDL and Verilog are two popular hardware description languages (HDL) used in both industry and academia.