Keywords: convolutional codes, power, register exchange, traceback, viterbi decoder
The 1/2-rate Viterbi decoder
with 5-bit soft coding presented in  requires a logic area of approx.
Using the branch metric and Viterbi decoder
algorithm, the conceptual structure of coherent RAKE receiver architecture for DSSS-CPM is shown in Figure 3.
For accomplishing this, firstly a Viterbi decoder
is implemented and after that its performance is enhanced to handle error prone communications over noisy and deep space channels.
In the Aircraft Downlink Receiver' the Viterbi Decoder
block decodes input symbols to produce binary output symbols.
The table shows that a large percentage of the ALU operations are centralized on the modules of the synchronizer and Viterbi decoder
The Viterbi decoder
 examines an entire received sequence of a given length.
Give the received data to the Viterbi decoder
DSP functions used in communications subsystems such a FEC 32-channel Viterbi decoder
core can now be implemented in a Spartan-3 FPGA (XC3S1000) for an effective price of $0.14 per channel.
. The decoded symbols are then verified by using CRC bits.
Typically, the bit error rate (BER) is within 0.4 dB of theoretical, as shown in Figure 1, where the theoretical plot is for an eight-level, K = 7 Viterbi decoder
(used in the receiver).
Parhi, "Interleaved Convolutional Code and Its Viterbi Decoder
Architecture," EURASIP Journal on Applied Signal Processing, vol.