Viterbi decoder


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Viterbi decoder

A decoding algorithm developed in the late 1960s by Andrew Viterbi that is used to decode a particular convolutional code. Viterbi decoders have been the most effective way to decode wireless voice communications in satellite and cellphone transmissions. Viterbi outputs a 0 or a 1 based on its estimate of the input bit. See CDMA, convolutional code and turbo code.


Using the Viterbi Decoder
In the CDMA technology, the Viterbi decoder in the cellphone is used to correct the errors in the convolutional code that was generated by the base station. See CDMA.
References in periodicals archive ?
Keywords: convolutional codes, power, register exchange, traceback, viterbi decoder
The 1/2-rate Viterbi decoder with 5-bit soft coding presented in [20] requires a logic area of approx.
Using the branch metric and Viterbi decoder algorithm, the conceptual structure of coherent RAKE receiver architecture for DSSS-CPM is shown in Figure 3.
For accomplishing this, firstly a Viterbi decoder is implemented and after that its performance is enhanced to handle error prone communications over noisy and deep space channels.
In the Aircraft Downlink Receiver' the Viterbi Decoder block decodes input symbols to produce binary output symbols.
The table shows that a large percentage of the ALU operations are centralized on the modules of the synchronizer and Viterbi decoder.
The Viterbi decoder [1] examines an entire received sequence of a given length.
Give the received data to the Viterbi decoder for decoding.
DSP functions used in communications subsystems such a FEC 32-channel Viterbi decoder core can now be implemented in a Spartan-3 FPGA (XC3S1000) for an effective price of $0.14 per channel.
Viterbi decoder. The decoded symbols are then verified by using CRC bits.
Typically, the bit error rate (BER) is within 0.4 dB of theoretical, as shown in Figure 1, where the theoretical plot is for an eight-level, K = 7 Viterbi decoder (used in the receiver).
Parhi, "Interleaved Convolutional Code and Its Viterbi Decoder Architecture," EURASIP Journal on Applied Signal Processing, vol.