wafer scale integration

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wafer scale integration

The evolution in semiconductor technology that builds a gigantic circuit on an entire wafer. Just as the integrated circuit eliminated cutting apart thousands of transistors from the wafer only to wire them back again on circuit boards, wafer scale integration eliminates cutting apart the chips. All the circuits for an entire computer are designed onto one super-sized chip. See wafer.

In 1979, Trilogy attempted wafer scale integration with a 2.5 x 2.5" chip but failed to produce a product (see Trilogy). Since then, the multichip module (MCM) and multichip package (MCP), in which several chips are connected closely together in a single housing, has become widely used.

In 2019, Cerebras Systems developed its Wafer Scale Engine for deep learning applications (see Cerebras CS-1).
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References in periodicals archive ?
Among the topics are low-temperature bonding for optical microsystems applications, three-dimensional wafer-scale integration for radio frequency and digital applications, thick bonded silicon-on-insulator wafers with poly-silicon interlayer for gettering metal impurities, and an oxide-free silicon-to-silicon carbide hetero-bond.
If additional power were needed, several microturbines might operate in parallel, perhaps in integral arrays developed using wafer-scale integration techniques.