wait state


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wait state

[′wāt ‚stāt]
(computer science)
The state of a computer program in which it cannot use the central processing unit normally because the unit is waiting to complete an input/output operation.

wait state

(architecture)
A delay of one or more clock cycles added to a processor's instruction execution time to allow it to communicate with slow external devices. The number and duration of wait states may be pre-configured or they may be controlled dynamically via certain control lines.

wait state

The time spent waiting for an operation to take place. Wait states are often idle computer cycles, because a computer's CPU is much faster than main memory. Wait states are introduced between the time the CPU requests data from the RAM (an address is placed on the address bus) until the content has been delivered to the CPU. See address bus.
References in periodicals archive ?
What the user wants to do is avoid wait states between when a function is pressed and the screen responds.
The more processors we want to put on, the more wait states we incur, and the more performance we steal from each processor.
The processor runs at a certain speed, usually 10 to 33 MHz, with or without wait states (when the processor stops processing to catch up with slow memory).
RISC architecture limits are expected to be reached when it is no longer possible to get RAMs that are fast enough to read at one cycle and it becomes necessary to begin designing things like wait states into memory accesses.
Running from RAM with zero wait states, the benchmark cruises to a CoreMark/MHz in excess of 3.
Compared to previous 45nm technologies on record, the new platform reduces the leakage current that occurs when current is wasted in wait states to one-fifth that of previous levels and reduces interconnect-induced lag times by approximately 14%.
Based on the Intel 33-megahertz 80386 microprocessor, the Z-386/33E operates at zero wait states and is designed for disk-intensive applications in single and multi-user environments.
The AS8F2M32 offers an access time of 90 ns, allowing high-speed microprocessors to operate without wait states. To eliminate bus contention, the device has separate chip enable (CE\), write enable (WE\) and output enable (OE\) controls.
The no-wait feature eliminates the need for wait states between Read and Write operations.