write buffer

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Among the topics are reliable and real-time communication in industrial wireless mesh networks, mixed-criticality task synchronization in zero-slack scheduling, removing abstraction overhead in the composition of hierarchical real-time systems, scheduling analysis under fault bursts, cooperating write buffer cache and virtual memory management for flash memory based systems, timing analysis for resource access interference on adaptive resource arbiters, maximizing contention-free executions in multiprocessor scheduling, and mobile sensor navigation using rapid radio-frequency-based angle-of-arrival localization.
Both the 64 kb CAV24C64 and the 32 kb CAV24C32 feature 32 byte page write buffers, while the 2 kb CAV24C02, 4 kb CAV24C04, 8 kb CAV24C08 and 16 kb CAV24C16 incorporate a 16 byte page write buffer.
The operations with flash memory is: read continuous at the address (0xE8), read the buffer (0xd4), write in buffer 1 (0x84), write buffer 1 in flash memory (0x88), clear the memory in block mode (0x50), read a location of the address (0x08), read buffer 1 at the address (0xd4).
There are no write delays or maximum write buffer sizes.
Other features include high noise immunity, full array write protection, 64 Kb page write buffer and low power CMOS technology.
This allows the write buffer to vary in size as needed up to the size of the buffer pool.
The new core is a 32-bit microprocessor macrocell that combines the ARM9TDMI CPU core with 8k instruction and 8k data caches, instruction and data memory management units, a write buffer, an AMBA bus interface and an embedded trace macrocell interface.
Then, if a controller fails, its partner completes the write operations that were in process at the time of the failure by flushing its write buffer to disk, restoring the database to a consistent state.
The first chip to result from the alliance, the L7200, includes an ARM 720T processor core with 8Kbyte cache, write buffer and memory management unit, along with several integrated AMBA (Advanced Microcontroller Bus Architecture) peripherals.
Other features of the new architecture include a new Instruction Fetch Unit (IFU), an Address and Data Unit (ADU), support for Dual-Port RAM, a Write Buffer and three register banks.
Once two devices on the bus have negotiated a speed, the initiator sends out a Write Buffer command to the device to test transfers at the negotiated speed.