In this state, the address of the data from external ROM is fetched first for which "ale" is asserted to latch lower order
address bus. Then the control branches to state 501, where the "ale" signal is deactivated.
The two least significant bits of
address bus (LSB) are entries for one block of Cache RAM, this block is called LSB Control, aspect presented in fig.
The address and slot map for each channel are connected to a common
address bus. This bus bypasses the register files and directly drives the backplane transceivers during bus address cycles.
[2] also looked at combining a serialized-widened bus with differential data encoding and found that it helped on the
address bus but not on the data bus.
The microcontroller has an 8-bit data bus and a 16-bit
address bus, allowing the use of 64KB of external memory.