gate array
An earlier type of ASIC chip that was partially finished with rows of unconnected transistors and resistors. The chip was completed by designing and adhering the top metal layers that provided the interconnecting pathways to form logic gates (NAND, NOR, etc.). These final masking stages were less costly than designing a full custom chip from scratch, which requires a new photo-mask for every transistor and interconnection layer. Gate arrays were superseded by field programmable gate arrays (see FPGA).Basic Cells
The gate array was made up of cells containing a number of transistors and resistors. Using a cell library (gates, registers, etc.) and a macro library (more complex functions), the customer designed the chip, and the vendor's software generated the interconnection masks. Quite often, many cells went unused. See ASIC, PLD, hard macro and soft macro.
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| Gate Array Cells |
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| These are examples of basic cells, one for CMOS only and another for CMOS and bipolar transistors. See CMOS and bipolar transistor. |
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