structured ASIC

structured ASIC

A type of application specific IC (ASIC) chip that contains blocks of logic, called "tiles" or "modules," that have their transistors already wired together forming gates along with some combination of multiplexors, flip/flops, look up tables and the like. Some vendors also include blocks of RAM. Unlike a standard cell, which requires all the masking stages in the transistors and metallization layers to be fabricated, structured ASICs require only one or two masks to tie the tiles together. In one design, only the vias need to be made conductive in order to complete the chip. See ASIC and via.

Copyright © 1981-2025 by The Computer Language Company Inc. All Rights reserved. THIS DEFINITION IS FOR PERSONAL USE ONLY. All other reproduction is strictly prohibited without permission from the publisher.