address bus


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address bus

[′ad·res ‚bəs]
(computer science)
An internal computer communications channel that carries addresses from the central processing unit to components under the unit's control.

address bus

(processor)
The connections between the CPU and memory which carry the address from/to which the CPU wishes to read or write. The number of bits of address bus determines the maximum size of memory which the processor can access.

See also data bus.

address bus

An internal channel from the CPU to memory across which the addresses of data (not the data) are transmitted. The number of lines (wires) in the address bus determines the amount of memory that can be directly addressed as each line carries one bit of the address. For example, a 20-line address bus represents the binary number 1,048,576 and reaches that number of memory bytes (the size of the address bus in the IBM PC in 1981). A computer with a 32-bit address bus can directly address 4GB of physical memory, while one with 36 bits can address 64GB.


References in periodicals archive ?
In this state, the address of the data from external ROM is fetched first for which "ale" is asserted to latch lower order address bus.
The two least significant bits of address bus (LSB) are entries for one block of Cache RAM, this block is called LSB Control, aspect presented in fig.
Using microcontrollers with large address bus and higher resolution.
Figure 1 shows a program that triggers when the duration between the INTERRUPT line going low and an Address bus match exceeds a given time, which could be used to determine if interrupt handling latency exceeds a specified time.
Concurrent read and write operation -- Unidirectional read and write interfaces -- Single address bus -- 18 pin DDR data output path transfers 32 bits + 4 bits of even byte parity per read -- 18 pin DDR data input path transfers 32 bits + 4 bits of even byte parity per write
Defined with minimal overhead, the Atlantic interface utilizes approximately 10 control signals in addition to a variable width data bus, and an optional address bus.
Defined with minimal overhead, Atlantic utilizes approximately 10 control signals in addition to a variable width data bus, and an optional address bus.
MIPS instruction set -- 36-bit address bus (64-bit virtual address), 64-bit data bus -- 8KB instruction cache, 8KB data cache with 8-bit error detection & correction -- 25MHz pipeline frequency -- 50MHz external clock (a selectable feature for the bus clock rate) -- 64-bit general-purpose registers, integer unit, floating point registers, and floating point unit -- Operating voltage of 3.
6 Gigabyte-per-second address bus for massive scalability; support for a large 8 Megabyte Error Checking and Correcting (ECC)-protected external cache; and a new error isolation and correction "Uptime Bus" for high-system reliability.
3DSP's new bus controller can support up to 15 simultaneous data transfers with zero overhead arbitration and has a single data bus and an address bus shared among peripherals.