addressing mode

[ə′dres·iŋ ‚mōd]

(computer science)

The specific technique by means of which a memory reference instruction will be spelled out if the computer word is too small to contain the memory address.

addressing mode

(processor, programming)

One of a set of methods for specifying the operand(s) for a machine code instruction. Different processors vary greatly in the number of addressing modes they provide. The more complex modes described below can usually be replaced with a short sequence of instructions using only simpler modes.

The most common modes are "register" - the operand is stored in a specified register; "absolute" - the operand is stored at a specified memory address; and "immediate" - the operand is contained within the instruction.

Most processors also have indirect addressing modes, e.g. "register indirect", "memory indirect" where the specified register or memory location does not contain the operand but contains its address, known as the "effective address". For an absolute addressing mode, the effective address is contained within the instruction.

Indirect addressing modes often have options for pre- or post- increment or decrement, meaning that the register or memory location containing the effective address is incremented or decremented by some amount (either fixed or also specified in the instruction), either before or after the instruction is executed. These are very useful for stacks and for accessing blocks of data. Other variations form the effective address by adding together one or more registers and one or more constants which may themselves be direct or indirect. Such complex addressing modes are designed to support access to multidimensional arrays and arrays of data structures.

The addressing mode may be "implicit" - the location of the operand is obvious from the particular instruction. This would be the case for an instruction that modified a particular control register in the CPU or, in a stack based processor where operands are always on the top of the stack.

addressing mode

(2)

In IBM System 370/XA the addressing mode bit controls the size of the effective address generated. When this bit is zero, the CPU is in the 24-bit addressing mode, and 24 bit instruction and operand effective addresses are generated. When this bit is one, the CPU is in the 31-bit addressing mode, and 31-bit instruction and operand effective addresses are generated.

["IBM System/370 Extended Architecture Principles of Operation", Chapter 5., 'Address Generation', BiModal Addressing].

References in periodicals archive ?

Post-indexed addressing mode example: (a) C program, (b) Assembly program There are very few unused opcodes available in Thumb.

The second is immediate post-indexed addressing mode (bit 6=1).

A few of the least frequent instructions need to be reduced to provide encoding space for the new addressing modes. In the instruction selection, the number of operand bits is first considered because each new addressing mode requires 10 bits for the operands and the AMEX16 mode as shown in Fig.

In this paper, we realize the importance of the addressing mode, and extend the addressing mode of the 16-bit Thumb architecture, which enables performance improvement of an average of 7.0% compared to the 16-bit Thumb instruction set architecture.

To fit into the 16-bit encoding space, the 16-bit Thumb ISA reduces the number of both accessible registers and addressing modes. This reduction limits the number of 32bit ARM instructions that can be converted into the 16-bit Thumb format, thereby reducing both compression efficiency and performance.

Addressing Mode Extension to the ARM/Thumb Architecture

For example, the Pentium uses a "ModR/M" byte to specify addressing modes and an "SIB" byte to identify index registers [Intel Corp.

To demonstrate the utility of our specification language, we show two complex aspects of our Pentium specification: addressing modes and variable-sized operands.

The first group of constructors specifies the nonindexed addressing modes. The simplest mode is encoded by rood = 3; it is a register-direct mode that can refer to any of the machine's 8 general registers.

None of the addressing modes specifies a value for the reg_opcode (middle) field of the ModR/M token.

Some addressing modes have different representations, depending on where they are used; currently, they must be associated with distinct sets of constructors of distinct types.

Specifying representations of machine instructions

Branch instructions use the standard addressing modes, as defined in Figure 2, where the R2 field holds the condition code field that specifies the type of branch.

The Clipper (TM) Processor: instruction set architectures and implementation

CISC--Complex instruction set computer, characterized by variable-length instructions, a wide variety of memory addressing modes, and instructions that combine one or more memory accesses with arithmetic.