antifuse


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antifuse

A programmable chip technology that creates permanent, conductive paths between transistors. In contrast to "blowing fuses" in the fusible link method, which opens a circuit by breaking apart a conductive path, the antifuse method closes the circuit by "growing" a conductive via. Two metal layers sandwich a layer of non-conductive, amorphous silicon. When voltage is applied to this middle layer, the amorphous silicon is turned into polysilicon, which is conductive.


Connect the Lines
The antifuse technology creates closed circuits by turning non-conductive silicon into a conductive via.
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References in periodicals archive ?
McCollum, "ASIC versus antifuse FPGA reliability," in Proceedings of the IEEE Aerospace Conference, pp.
Microsemi's Axcelerator FPGAs are the commercial equivalent of Microsemi's space-flight RTAX-S/SL FPGAs and share the same CMOS structures, antifuse technology, materials, processing, dimensions and programming attributes.
Electrical Embedded Antifuse Fuse EEPROM/Flash Technology Poly Fuse Charge Trapping Oxide breakdown Additional Step 0 8-15 0 Scalability Yes Up to 90nm Yes Security None Medium+ High Viable for SIM Card?
The probing capability associated with antifuse FPGAs is related to the need to select any of the antifuses for programming.
[USPRwire, Sun Feb 28 2016] FPGA Market by Type (High-End, Mid-End, Low-End), Verticals (Telecommunication, Industrial, A&D, Automotive, & Others), Architecture (Sram, Flash, & Antifuse), Technology Node (28nm-10nm, 45/40nm, & Others), and Geography - Forecast to 2022
There are three main types of nonvolatile FPGAs: flash, antifuse and SRAM with on-chip configuration memory.
The company said that it now stocks IGLOO and SmartFusion FPGAs for industrial and consumer applications, as well as antifuse devices for high-reliability, defence and aerospace customers.
Today, designers can use FPGAs based on any of three very different technologies: SRAM, flash and antifuse.
Except for few large complex PLDs, PLDs [34] are typically configured by EEPROMs or silicon antifuses, whereas FPGAs are configured by SRAMs.