It utilizes Kilopass Technology's patented 2T
antifuse bitcell with proven security that is critical for secure code storage applications.
McCollum, "ASIC versus
antifuse FPGA reliability," in Proceedings of the IEEE Aerospace Conference, pp.
Microsemi's Axcelerator FPGAs are the commercial equivalent of Microsemi's space-flight RTAX-S/SL FPGAs and share the same CMOS structures,
antifuse technology, materials, processing, dimensions and programming attributes.
Electrical Embedded
Antifuse Fuse EEPROM/Flash Technology Poly Fuse Charge Trapping Oxide breakdown Additional Step 0 8-15 0 Scalability Yes Up to 90nm Yes Security None Medium+ High Viable for SIM Card?
The probing capability associated with
antifuse FPGAs is related to the need to select any of the
antifuses for programming.
[USPRwire, Sun Feb 28 2016] FPGA Market by Type (High-End, Mid-End, Low-End), Verticals (Telecommunication, Industrial, A&D, Automotive, & Others), Architecture (Sram, Flash, &
Antifuse), Technology Node (28nm-10nm, 45/40nm, & Others), and Geography - Forecast to 2022
There are three main types of nonvolatile FPGAs: flash,
antifuse and SRAM with on-chip configuration memory.
Microsemi is committed to the longevity of our products and is pleased Avnet has exclusive rights to distribute our ACT 1, ACT 2 and ACT 3
antifuse devices, which have experienced more than two decades of success serving the market with their unique capabilities, said Andrew Girardi, senior director of business operations at Microsemi.
The company said that it now stocks IGLOO and SmartFusion FPGAs for industrial and consumer applications, as well as
antifuse devices for high-reliability, defence and aerospace customers.
Today, designers can use FPGAs based on any of three very different technologies: SRAM, flash and
antifuse.
To enable this study, the CEA would like to purchase the following items - Access to a front end design kit for FDSOI CMOS 14 nm and Flip Chip technology,- Elements library (standard cells, I / O, bumps, ESD cells, spare cell, etc..)- Access to complex programmable PLL IP (400-1600 MHz) and temperature sensor,- Access to memory type libraries
antifuse RAM SPREG type REPMB for different capacities,- Access to a sign-off kit including environment-placement and routing type checking DRC, ANT, LVS, etc..
Except for few large complex PLDs, PLDs [34] are typically configured by EEPROMs or silicon
antifuses, whereas FPGAs are configured by SRAMs.
