branch prediction


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branch prediction

[′branch prə‚dik·shən]
(computer science)
A method whereby a processor guesses the outcome of a branch instruction so that it can prepare in advance to carry out the instructions that follow the predicted outcome.

branch prediction

(processor, algorithm)
A technique used in some processors with instruction prefetch to guess whether a conditional branch will be taken or not and prefetch code from the appropriate location.

When a branch instruction is executed, its address and that of the next instruction executed (the chosen destination of the branch) are stored in the Branch Target Buffer. This information is used to predict which way the instruction will branch the next time it is executed so that instruction prefetch can continue. When the prediction is correct (and it is over 90% of the time), executing a branch does not cause a pipeline break.

Some later CPUs simply prefetch both paths instead of trying to predict which way the branch will go.

An extension of the idea of branch prediction is speculative execution.

branch prediction

In CPU instruction execution, predicting the outcome of a branch so that those instructions may be executed in parallel with the current instructions. If the CPU guesses the wrong branch, it will take extra machine cycles to go back and execute the correct one; however, on average, if the prediction algorithms are good, overall performance is increased. See predication and branch.
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References in periodicals archive ?
Section 6 presents a performance analysis and finally, section 7 gives conclusions and suggested future dynamic branch prediction development.
A shadow dynamic finite state machine for branch prediction: an alternative for the 2-bit saturating counter
The first proposal of this Thesis is the Branch Prediction Reversal Unit (BPRU), a mechanism that selectively reverses those branch predictions likely to be mispredicted in order to improve branch prediction accuracy.
Reducing branch misprediction penalty through confidence estimation
1999] to identify representative sections of the program run based on cache and branch prediction statistics, we then simulate a 100 million instruction window using the detailed simulator.
Value-Based Clock Gating and Operation Packing: Dynamic Strategies for Improving Processor Power and Performance
A branch prediction scheme that exploits branch correlation requires more detailed execution information than that provided by traditional (point) profiles.
Static Correlated Branch Prediction
Briefly, multiple branch prediction anticipates jumps in the instruction flow, data flow analysis determines the optimal sequence for instruction processing; and speculative execution is a method of looking ahead for useful work to perform.
Shipping boxes: Pentium-based systems for 1996 and 1997
Keywords: Branch Prediction, Two-Level Predictor, Gshare, Generalized Branch Predictor
Improving branch prediction performance with a generalized design for dynamic branch predictors
Tag comparison, branch prediction, and instruction decode are outside the critical fetch loop [5].
Fetch unit design for scalable simultaneous multithreading (ScSMT)
Moreover, even though both value prediction and branch prediction use a similar technology, there are fundamental differences between the goals of these mechanisms.
Using Value Prediction to Increase the Power of Speculative Execution Hardware
Additional Key Words and Phrases: Branch prediction, decision trees, machine learning, neural networks, performance evaluation, program optimization
Evidence-based static branch prediction using machine learning
Most implementations of the PowerPC Architecture implement some form of branch prediction in order to minimize potential delays associated with control flow instructions.
A modular approach to Motorola PowerPC compilers
ARC was able to achieve clock speeds of 400MHz and above through a sophisticated pipeline structure that supports out-of-order completion, non-blocking access, 2-level hit-under-miss scheduling, and configurable dynamic branch prediction for maximum throughput.
ARC 700 Raises the Bar for High Performance, Low Gate Count Processors; World's Smallest 400MHz RISC/DSP Processor
This last isn't a brand-new feature, but companies are often cagey about the exact details of how they implement branch prediction in silicon.
Samsung May Be in Talks with AMD, Nvidia to License Graphics IP

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