bus cycle

bus cycle

[′bəs ‚sī·kəl]
(computer science)
A single transaction between the main memory and the CPU.
References in periodicals archive ?
An intelligent system, it is designed to be employed in a Master-Slave system where a single AS-Interface Master can exchange I/O data with up to 62 AS-Interface Slave devices and each Slave can transfer up to four inputs and four outputs on a bus cycle.
The E100 works with new and future devices in the M16C, H8SX, H8S, H8, and R8C families of 8- to 32-bit CISC (Complex Instruction Set Computer) devices and allows real-time in-circuit emulation at bus cycle speeds up to 130MHz.
Additional bus support features include 4-state real-time nested event detection for single thread events on each bus cycle and real-time trace.
Synchronization modes operate at the clock edge, clock cycle, bus cycle, instruction cycle, function level and program level as well as fully asynchronous operation.
Hardware design teams will want to take advantage of this free evaluation to experiment with the clock-cycle accurate, pipeline-modeling instruction set simulator and the associated performance modeling visualization views within the graphical user interface that show pipeline activity, cache utilization rates, and cycles spent on bus cycle activity.
Additional bus support features include 4-state, real-time nested event detection for a single thread event on each bus cycle and real-time trace.
97MHz operating speed now allows a minimum bus cycle of 100nS (nanoseconds) for faster instruction execution.
With large memory buffers containing fine granularity, fast bus cycle times and built-in support for flow control, the LAN9118 can support extremely high data rates with little or no packet loss.
Maintaining 32-bit widths on both the address and data bus as well as the bursting protocol for cacheable memory, the 68060 supports transfers of one, two, four or 16 bytes in a given bus cycle.
Users can purchase a software upgrade for $695 that includes the performance analysis features, deeper on-chip trace support, including bus cycle information, and additional hardware triggers.
In lab tests running UDDS, Steady State and NYC Bus Cycle modes the Rentar demonstrated superior fuel savings ranging from 5.
Novas has developed an intuitive environment for transaction waveform viewing, protocol checking, and bus cycle analysis that eases debug of standard (e.