bus cycle

bus cycle

[′bəs ‚sī·kəl]
(computer science)
A single transaction between the main memory and the CPU.
References in periodicals archive ?
Working with TfL led to the development of the Millbrook London Transport Bus Cycle (MLTB), used to evaluate all buses purchased on behalf of the authority.
HBM says enabling torque and rotational speed signals as well as angle of rotation and power to be digitally transmitted to PROFINET, the hardware supports Real Time Classes RT Class 1 and RT Class 3 (IRT) with a bus cycle time of up to 4 kHz.
An intelligent system, it is designed to be employed in a Master-Slave system where a single AS-Interface Master can exchange I/O data with up to 62 AS-Interface Slave devices and each Slave can transfer up to four inputs and four outputs on a bus cycle.
Since a bus cycle takes two clocks, the phase signal is used to identify the first clock period.
For the current family of Intel processors, it takes two processor cycles to execute one bus cycle (P/B ratio).