bus master

bus master

(architecture)
The device in a computer which is driving the address bus and bus control signals at some point in time. In a simple architecture only the (single) CPU can be bus master but this means that all communications between ("slave") I/O devices must involve the CPU. More sophisticated architectures allow other capable devices (or multiple CPUs) to take turns at controling the bus. This allows, for example, a network controller card to access a disk controller directly while the CPU performs other tasks which do not require the bus, e.g. fetching code from its cache.

Note that any device can drive data onto the data bus when the CPU reads from that device, but only the bus master drives the address bus and control signals.

Direct Memory Access is a simple form of bus mastering where the I/O device is set up by the CPU to read from or write to one or more contiguous blocks of memory and then signal to the CPU when it has done so. Full bus mastering (or "First Party DMA", "bus mastering DMA") implies that the I/O device is capable of performing more complex sequences of operations without CPU intervention (e.g. servicing a complete NFS request). This will normally mean that the I/O device contains its own processor or microcontroller.

See also distributed kernel.
References in periodicals archive ?
Other features include two serial ports, four USB ports, a PCI Bus Master 10/100Base-TX Ethernet controller and support for up to 512MB DDR SDRAM.
In addition QuickLogic offers a variety of hot swappable PCI bridge ASSPs including 32-bit system master, bus master, bus target, and stand-alone target for 33 MHz and 50 MHz PCI busses, with internal bus speeds ranging from 33 MHz to 75 MHz.
Four I2C serial interface bus master controllers and two UARTs assist in firmware development and out-of-band communication via the Intelligent Platform Management Interface (IPMI).
The Hurricane Board can be configured to work in the following modes: system master, PCI bus master and PCI bus target.