cache coherency


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cache coherency

(storage)
(Or "cache consistency") /kash koh-heer'n-see/ The synchronisation of data in multiple caches such that reading a memory location via any cache will return the most recent data written to that location via any (other) cache.

Some parallel processors do not cache accesses to shared memory to avoid the issue of cache coherency. If caches are used with shared memory then some system is required to detect when data in one processor's cache should be discarded or replaced because another processor has updated that memory location. Several such schemes have been devised.

cache coherency

Managing a cache so that data are not lost or overwritten. For example, when data are updated in a cache but not yet transferred to the target memory or disk, the chance of corruption is greater. Accomplished by well-designed algorithms that keep track of every read and write event, cache coherency is even more critical in symmetric multiprocessing (SMP) where memory is shared by multiple processors. See cache and SMP.
References in periodicals archive ?
Mattson has argued that a better approach would be to eliminate cache coherency and instead allow cores to pass messages among one another.
Enabling this cache coherency through a large cluster requires extremely efficient communication between all nodes.
The cache coherency is not maintained effectively and consistently.
Smart MP technology also has an optimized Modified Owner Exclusive Shared Invalid (MOESI) cache coherency protocol that manages data and memory traffic in a multiprocessing environment.
1990] presented an algorithm for determining the earliest time when it is safe to prefetch shared data in a multiprocessor with software-controlled cache coherency. Since the prefetches are binding, all control and data dependencies must be carefully considered.