cache line


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cache line

(storage)
(Or cache block) The smallest unit of memory than can be transferred between the main memory and the cache.

Rather than reading a single word or byte from main memory at a time, each cache entry is usually holds a certain number of words, known as a "cache line" or "cache block" and a whole line is read and cached at once. This takes advantage of the principle of locality of reference: if one location is read then nearby locations (particularly following locations) are likely to be read soon afterward. It can also take advantage of page-mode DRAM which allows faster access to consecutive locations.

cache line

The block of memory that is transferred to a memory cache. The cache line is generally fixed in size, typically ranging from 16 to 256 bytes. The effectiveness of the line size depends on the application, and cache circuits may be configurable to a different line size by the system designer. There are also numerous algorithms for dynamically adjusting line size in real time. See cache.
References in periodicals archive ?
Besides, with [T.sub.C] representing the time used for copying a memory block which maps to a single cache line, [T.sub.CP] can then be expressed as:
Caption: Figure 8: Cache line pattern of [k.sub.0] = 0xf_ (a) for clean CSCa implementation (b) for the CSCa with a reduced probe frequency.
This technique states that we should replace the cache line that has not been accessed for the longest period.
In this paper there are analyzed important technical aspects that can influence the overall performance of an application developed for CUDA enabled GPUs: the increased speedup offered by putting into use the shared and cache memory; the alignment of data in memory; optimal memory access patterns; aligning to the L1 cache line; the balance achieved between single or double precision and its effect on memory usage; joining more kernel functions into a single one; adjusting the code to the available memory bandwidth in accordance with the memory latency and the necessity to transfer data between the host and the device.
When occurs the cache line loading from dynamic RAM, the two LSB bits, are obtained from the numerator, which increments the address with four locations.
Interference occurs in the cache system when data belonging to one thread is evicted by a cache line from another thread.
The most sophisticated of the external cache systems also offer the ability to flexibly configure the cache line size to match the size of incoming data traffic and to control the rate at which data is flushed to attached RAID systems.
Sun is also going to increase the number of transistors dedicated to L2 memory tags by a factor of eight in the Jaguar kickers while shortening the cache line size from 512 bytelines to 128 bytelines.
The two-way set-associative caches are nonblocking and support cache line locking.
We assume the following in these examples: a cache line is 32 bytes long; an instruction is four bytes long (hence one cache line contains eight instructions); hardware next-8-line prefetching is enabled; and the prefetching distance is 20 instructions.
In a direct-mapped cache, the relationship between the memory address and the cache line number is simply