On the other hand, long cache miss
latencies of directory protocols are caused by the inefficiencies that the distributed nature of the protocols and the underlying scalable network imply.
2 L1 Cache miss
rates for the SPARC machine (OB--miss rate for the compilation-Optimized 16 x 16 Blocked; OL--miss rate for the compilation-Optimized 16 x 16 data Laid; Imp--percentage miss rate improvement of the data laid version over the blocked version) Grid Size OB OL Imp 33 x 32 0.
Our experimental results (sections 5 and 6) show that more than 8 threads can increase cache miss
rate too much, so we assume a maximum of 8 threads.
In the event of a thread's cache miss
, that specific thread is not issued again until its cache miss
is fully serviced.
The system uses adaptive cache algorithms that help to decrease the cache miss
rate, all of which ultimately require statistical feedback, such as most frequently-accessed documents, most frequently-requested search terms, etc.