capacitive load

capacitive load

[kə¦pas·əd·iv ¦lōd]
(electromagnetism)
A load in which the capacitive reactance exceeds the inductive reactance; the load draws a leading current.
References in periodicals archive ?
device for the protection of the dsl line aml (ultrasound dsl) (reaction time per renar to 5 ns; capacitive load per line up to 100 pf;
Most remarkable, the device delivers 1,000 Amps almost perfect rectangular wave pulses with matching rising and falling slopes, even on a capacitive load, faster than 160ns with "G" series switches and 78ns or faster with the "F" series switches.
After extensive testing by Hill, it was determined that the matrix is capable of handling the capacitive load seen on the A-10C, and the module performed as required.
For performance in driving inkjet printer heads comprised of multiple nozzles, the output signal for the MP106 is virtually independent from the capacitive load to ensure consistent print quality.
This solution also makes it possible to remove the question of the effect of the capacitive load of the measuring device on the coefficient of conversion of the voltage divider.
Similarly, for inductive to capacitive load, the proposed Enhanced PQ with average algorithm also shows the best performance with response time of 0.025 s and no undershoot.
In selecting the capacitive load to the secondary winding in the circuit of the transformer we have used the capacitor values as shown in Figure 8.
Figure 8 indicates the frequency response of the proposed circuit for 80 pF capacitive load. Phase margin of the circuit is 89.44[degrees].
During the isolation time, the inverter output is in a high-impedance state (indicated by the grayed output signal areas in timing diagram in Figure 1(b)), preserving the old logical state on capacitive load and preventing the direct-path current from flowing between the power supply and the ground.
* Fast 39 us propagation delay times and 20 ns driver rise/fall times for a 1 1-1F capacitive load.
In case of added capacitive load, we take the capacitance as ([C.sub.p[+[C.sub.l]), where [C.sub.p] is the intrinsic capacitance of the transistor and Cl is the added capacitive load at each level.
We propose and design the padless PTH via to further reduce the capacitive load from the conventional pads at the via-ends.