chiplet


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chiplet

A future semiconductor technology from Palo Alto Research Center (PARC), a subsidiary of Xerox, that ties together minuscule circuits no larger than a grain of sand to make microprocessors, memory and other electronic components. Introduced in 2013, PARC's "Xerographic micro-assembly" cuts a wafer into tens of thousands of chiplets rather than hundreds of chips as in the traditional semiconductor process. The chiplets can be wrapped around flexible surfaces and may even become the "ink" in 3D printing.

More than a decade ago, Alien Technologies developed a similar technology. The tiny chips in Alien's Fluid Self Assembly (FSA) were named "Nanoblocks." The patented Fluid Self Assembly is waiting in the wings for the time it becomes commercially viable. See 3D printing, chip, wafer and PARC.
References in periodicals archive ?
The new technology involves etching a pit of the correct depth and size in the surface of a silicon wafer, then inserting a tiny patterned chip (sometimes called a "chiplet") into the pit.
Bill Chappell, director of DARPA's Microsystems Technology Office, when introducing the CHIPS program, said, 'By bringing the best design capabilities, reconfigurable circuit fabrics, and accelerators from the commercial domain, we should be able to create defence systems just by adding smaller specialised chiplets.'
An interesting tidbit in Foveros is the introduction of "chiplets," which basically is the fragmentation of CPU into its individual parts.
Tenders are invited for Supply Of Butter Chiplets To Hotel Janpath New Delhi
The base die, compute chiplets, and DRAM layers are all stacked one on top of the other.
A number of companies have proposed a strategy of chiplets to achieve the economics of scaling previously achieved with silicon scaling.
It has a base clock of 3.8 GHz and a boost clock of 4.6 GHz and uses two chiplets to achieve the high core count.
Netronome is collaborating with six silicon companies, Achronix, GLOBALFOUNDRIES, Kandou, NXP, Sarcina and SiFive, to develop an open architecture and related specifications for developing chiplets that promise to reduce silicon development and manufacturing costs.